Integrated circuit

• US 9,363,053 B2
• Filed: 08/25/2015
• Issued: 06/07/2016
• Est. Priority Date: 08/05/2005
• Status: Active Grant

• Current Assignee: Panasonic Holdings Corporation
• Original Assignee: Panasonic Intellectual Property Corporation of America (Panasonic Holdings Corporation)
• Inventors: Miyoshi, Kenichi, Suzuki, Hidetoshi, Hiramatsu, Katsuhiko, Wengerter, Christian, Golitschek Edler Von Elbwart, Alexander
• Primary Examiner(s): Timory, Kabir A
• Application Number:
  US14/834,909
• Publication Number:
  US 20150365210A1
• Time in Patent Office: 287 Days
• Field of Search: 375/298, 375/295, 375/308, 375/324, 375/329, 375/340
• US Class Current: 1/1
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 15/00 Suppression or limitation of noise or interference by means associated with receiver H04B1/10
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 25/0202 Channel estimation
• CPC Class Codes: H04L 25/0212 of impulse response
• CPC Class Codes: H04L 25/0224 using sounding signals
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/183 Multiresolution systems
• CPC Class Codes: H04L 27/34 Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
• CPC Class Codes: H04L 27/36 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 5/0046 Determination of how many bits are transmitted on different sub-channels

Abstract

Wireless communication wherein channel estimation accuracy is improved while keeping the position of each bit in a frame, even when a modulation system having a large modulation multiple value is used for a data symbol. An encoding operation encodes and outputs transmitting data (bit string) and a bit converting operation converts at least one bit of a plurality of bits constituting a data symbol to be used for channel estimation, among the encoded bit strings, into ‘1’ or ‘0’. A modulating operation modulates the bit string inputted from the bit converting operation by using a single modulation mapper and a plurality of data symbols are generated.

Claims

1. An integrated circuit comprising:

generating circuitry which, in operation, generates a bit sequence by forcibly setting each of at least lowest two bits of a plurality of bits to a 1, the plurality of bits forming a modulation symbol in the bit sequence; and

modulating circuitry which, in operation, modulates the bit sequence by mapping the plurality of bits on a single modulation mapper, wherein the single modulation mapper has 16 first signal points for 16 QAM,

wherein each of the lowest two bits of the plurality of bits is forcibly set to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of first signal points, a distance between the second signal points being equivalent to largest distances existing among the first signal points in an I-Q plane of the single modulation mapper.

2. The integrated circuit according to claim 1, comprising:

at least one input coupled to the generating circuitry, wherein the at least one input, in operation, inputs data; and

at least one output coupled to the modulating circuitry, wherein the at least one output, in operation, outputs data.

3. The integrated circuit according to claim 2, wherein the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

4. The integrated circuit according to claim 2, wherein the bit sequence is generated by forcibly setting each of the lower four bits of the plurality of bits to the 1.

5. The integrated circuit according to claim 2, wherein the bit sequence is generated by forcibly setting each of the lowest three bits of the plurality of bits to the 1.

6. The integrated circuit according to claim 2, wherein the at least one output and the at least one input, in operation, are coupled to an antenna.

7. An integrated circuit comprising:

generating circuitry which, in operation, generates a bit sequence by forcibly setting each of at least lowest two bits of a plurality of bits to a 1, the plurality of bits forming a modulation symbol in the bit sequence; and

modulating circuitry which, in operation, modulates the bit sequence by mapping the plurality of bits on a single modulation mapper to generate a plurality of modulation symbols, wherein the single modulation mapper has 16 first signal points for 16 QAM,

wherein each of the lowest two bits of the plurality of bits is forcibly set to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of first signal points, such that said modulation symbol is detected only by a decision of whether the modulation symbol is positive or negative with respect to at least one of an I-axis and a Q-axis in the single modulation mapper.

8. The integrated circuit according to claim 7, comprising:

at least one input coupled to the generating circuitry, wherein the at least one input, in operation, inputs data; and

at least one output coupled to the modulating circuitry, wherein the at least one output, in operation, outputs data.

9. The integrated circuit according to claim 8, wherein the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

10. The integrated circuit according to claim 8, wherein the bit sequence is generated by forcibly setting each of the lowest four bits of the plurality of bits to the 1.

11. The integrated circuit according to claim 8, wherein the bit sequence is generated by forcibly setting each of the lowest three bits of the plurality of bits to the 1.

12. The integrated circuit according to claim 8, wherein the at least one output and the at least one input, in operation, are coupled to an antenna.

13. An integrated circuit comprising:

at least one input; and

circuitry coupled to the at least one input, wherein the circuitry, in operation;

controls generating a bit sequence by forcibly setting each of at least lowest two bits of a plurality of bits to a 1, the plurality of bits forming a modulation symbol in the bit sequence; and

controls modulating the bit sequence by mapping the plurality of bits on a single modulation mapper, wherein the single modulation mapper has 16 first signal points for 16 QAM,

wherein each of the lowest two bits of the plurality of bits is forcibly set to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of first signal points, a distance between the second signal points being equivalent to largest distances existing among the first signal points in an I-Q plane of the single modulation mapper.

14. The integrated circuit according to claim 13, further comprising,

at least one output coupled to the circuitry, wherein the at least one output, in operation, outputs data.

15. The integrated circuit according to claim 14, wherein the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

16. The integrated circuit according to claim 14, wherein the bit sequence is generated by forcibly setting each of the lower four bits of the plurality of bits to the 1.

17. The integrated circuit according to claim 14, wherein the bit sequence is generated by forcibly setting each of the lowest three bits of the plurality of bits to the 1.

18. The integrated circuit according to claim 14, wherein the at least one output and the at least one input, in operation, are coupled to an antenna.

19. An integrated circuit comprising:

at least one input; and

circuitry coupled to the at least one input, wherein the circuitry, in operation;

controls generating a bit sequence by forcibly setting each of at least lowest two bits of a plurality of bits to a 1, the plurality of bits forming a modulation symbol in the bit sequence; and

controls modulating the bit sequence by mapping the plurality of bits on a single modulation mapper to generate a plurality of modulation symbols, wherein the single modulation mapper has 16 first signal points for 16 QAM,

wherein each of the lowest two bits of the plurality of bits is forcibly set to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of first signal points, such that said modulation symbol is detected only by a decision of whether the modulation symbol is positive or negative with respect to at least one of an I-axis and a Q-axis in the single modulation mapper.

20. The integrated circuit according to claim 19, further comprising,

at least one output coupled to the circuitry, wherein the at least one output, in operation, outputs data.

21. The integrated circuit according to claim 20, wherein the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

22. The integrated circuit according to claim 20, wherein the bit sequence is generated by forcibly setting each of the lowest four bits of the plurality of bits to the 1.

23. The integrated circuit according to claim 20, wherein the bit sequence is generated by forcibly setting each of the lowest three bits of the plurality of bits to the 1.

24. The integrated circuit according to claim 20, wherein the at least one output and the at least one input, in operation, are coupled to an antenna.