Vector processor having instruction set with sliding window non-linear convolutional function

• US 9,363,068 B2
• Filed: 01/30/2014
• Issued: 06/07/2016
• Est. Priority Date: 08/03/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Azadet, Kameran, Williams, Joseph, Yu, Meng-Lin
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US14/168,615
• Publication Number:
  US 20140317163A1
• Time in Patent Office: 859 Days
• Field of Search: 708/420, 708300-323
• US Class Current: 1/1
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/525 with means for reducing leakage of transmitter signal into the receiver
• CPC Class Codes: H04B 1/62 for providing a predistortion of the signal in the transmitter and corresponding correction in the receiver, e.g. for improving the signal/noise ratio
• CPC Class Codes: H04B 2001/0425 with linearisation using predistortion
• CPC Class Codes: H04J 11/004 using regenerative subtractive interference cancellation
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 25/03012 operating in the time domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/367 using predistortion
• CPC Class Codes: H04L 27/368 adaptive predistortion
• CPC Class Codes: H04L 5/1461 Suppression of signals in the return path, i.e. bidirectional control circuits

Abstract

A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.

Claims

1. A method performed by a processor, comprising:

obtaining at least one software instruction that performs at least one non-linear convolution function for a plurality of input delayed signal samples;

in response to said at least one software instruction for said at least one non-linear convolution function, performing the following steps;

generating a weighted sum of two or more of said input delayed signal samples, wherein said weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of said input delayed signal samples; and

repeating said generating step for at least one time-shifted version of said input delayed signal samples to compute a plurality of consecutive outputs, wherein said at least one software instruction for said at least one non-linear convolution function is part of an instruction set of said processor.

2. The method of claim 1, wherein said processor comprises a vector processor.

3. The method of claim 1, wherein said plurality of variable coefficients defined by a non-linear function of a magnitude of said input delayed signal samples are implemented using one or more look-up tables.

4. The method of claim 1, wherein said non-linear convolution function models a non-linear system with memory.

5. The method of claim 4, wherein said non-linear system with memory comprises one or more of a power amplifier model and a digital pre-distortion function.

6. The method of claim 1, wherein said at least one non-linear convolution function is implemented using one or more look-up tables having linear interpolation.

7. The method of claim 1, wherein said at least one non-linear convolution function is implemented using one or more look-up tables having polynomial interpolation.

8. The method of claim 1, further comprising the step of loading at least one user-specified parameter from memory into at least one register file.

9. The method of claim 8, wherein said user-specified parameter comprises a look-up table storing values of said non-linear convolution function for one or more input values.

10. The method of claim 1, further comprising the step of reading said plurality of input delayed signal samples directly from memory into functional units for said non-linear convolution function.

11. A processor configured to implement a signal processing function in software, comprising:

a memory; and

at least one hardware device, coupled to the memory, operative to;

obtain at least one software instruction that performs at least one non-linear convolution function for a plurality of input delayed signal samples;

in response to said at least one software instruction for said at least one non-linear convolution function;

generate a weighted sum of two or more of said input delayed signal samples, wherein said weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of said input delayed signal samples; and

repeat said generating step for at least one time-shifted version of said input delayed signal samples to compute a plurality of consecutive outputs, wherein said at least one software instruction for said at least one non-linear convolution function is part of an instruction set of said processor.

12. The processor of claim 11, wherein said processor comprises a vector processor.

13. The processor of claim 11, wherein said plurality of variable coefficients defined by a non-linear function of a magnitude of said input delayed signal samples are implemented using one or more look-up tables.

14. The processor of claim 11, wherein said non-linear convolution function models a non-linear system with memory.

15. The processor of claim 14, wherein said non-linear system with memory comprises one or more of a power amplifier model and a digital pre-distortion function.

16. The processor of claim 11, wherein said at least one non-linear convolution function is implemented using one or more look-up tables having linear interpolation.

17. The processor of claim 11, wherein said at least one non-linear convolution function is implemented using one or more look-up tables having polynomial interpolation.

18. The processor of claim 11, further comprising the step of loading at least one user-specified parameter from memory into at least one register file.

19. The processor of claim 18, wherein said user-specified parameter comprises a look-up table storing values of said non-linear convolution function for one or more input values.

20. The processor of claim 11, further comprising the step of reading said plurality of input delayed signal samples directly from memory into functional units for said non-linear convolution function.

21. An article of manufacture, comprising a non-transitory machine readable recordable medium containing one or more programs which when executed by a processor implement the steps of:

obtaining at least one software instruction that performs at least one non-linear convolution function for a plurality of input delayed signal samples;

in response to said at least one software instruction for said at least one non-linear convolution function, performing the following steps;

generating a weighted sum of two or more of said input delayed signal samples, wherein said weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of said input delayed signal samples; and

repeating said generating step for at least one time-shifted version of said input delayed signal samples to compute a plurality of consecutive outputs, wherein said at least one software instruction for said at least one non-linear convolution function is part of an instruction set of said processor.