Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
First Claim
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1. A clock recovery circuit, comprising:
- a receiver circuit adapted to decode data symbols from signals transmitted on a plurality of data lines, where at least one data symbol is encoded in state transitions of the signals transmitted on the plurality of data lines; and
a clock extraction circuit that obtains a clock signal from state transition signals derived from the state transitions while compensating for skew in different ones of the plurality of data lines, and masking data state transition glitches, wherein the clock extraction circuit uses a feedback delayed instance of a first state transition signal (SDRCLK) to obtain the clock signal.
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Abstract
A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions.
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Citations
24 Claims
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1. A clock recovery circuit, comprising:
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a receiver circuit adapted to decode data symbols from signals transmitted on a plurality of data lines, where at least one data symbol is encoded in state transitions of the signals transmitted on the plurality of data lines; and a clock extraction circuit that obtains a clock signal from state transition signals derived from the state transitions while compensating for skew in different ones of the plurality of data lines, and masking data state transition glitches, wherein the clock extraction circuit uses a feedback delayed instance of a first state transition signal (SDRCLK) to obtain the clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for recovering a clock signal, comprising:
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decoding data symbols from signals transmitted on a plurality of data lines, where at least one data symbol is encoded in state transitions of the signals transmitted on the plurality of data lines; and obtaining a clock signal from state transition signals derived from the state transitions while compensating for skew in different ones of the plurality of data lines, and masking data state transition glitches, wherein the clock signal is a feedback delayed instance of a first state transition signal (SDRCLK) that is used to obtain the clock signal. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A clock recovery circuit, comprising:
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means for decoding data symbols from signals transmitted on a plurality of data lines, where at least one data symbol is encoded in state transitions of the signals transmitted on the plurality of data lines; and means for obtaining a clock signal from state transition signals derived from the state transitions while compensating for skew in different ones of the plurality of data lines, and masking data state transition glitches, wherein the clock signal is a feedback delayed instance of a first state transition signal (SDRCLK) that is used to obtain the clock signal. - View Dependent Claims (23, 24)
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Specification