Clock-embedded vector signaling codes

• US 9,363,114 B2
• Filed: 03/02/2015
• Issued: 06/07/2016
• Est. Priority Date: 02/28/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin, Holden, Brian, Simpson, Richard
• Primary Examiner(s): HA, DAC V
• Application Number:
  US14/636,098
• Publication Number:
  US 20150249559A1
• Time in Patent Office: 463 Days
• US Class Current: 1/1
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828

Abstract

Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.

Claims

1. An apparatus comprising:

a global transmission encoder, accepting input data to be partitioned across two or more sub-channels of a communications channel and generating a set of reduced-modulus sub-channel transmit data;

communications sub-systems for each of the two or more sub-channels, each comprising;

a data history pre-coder accepting a respective one of the set of reduced-modulus sub-channel transmit data from the global transmission encoder and producing sub-channel transmit data based on the reduced modulus sub-channel transmit data and a prior codeword such that a signaling transition is provided by not retransmitting a given codeword in adjacent signaling intervals;

a data encoder encoding the sub-channel transmit data into codewords of a vector signaling code; and

,

a driver producing physical transmit signals representing the vector signaling code on the communications sub-channel.

2. The apparatus of claim 1, wherein the global transmission encoder performs a computation on the input data producing multiple results to be distributed among the two or more sub-channels.

3. The apparatus of claim 1, wherein each of the data history pre-coders maintains a history of at least one previous transmission interval to insure its sub-channel transmit data changes in each transmission interval.

4. The apparatus of claim 1, wherein the vector signaling code for each sub-channel is selected from a group consisting of:

Ensemble Non-Return to Zero (ENRZ), S3, OCT, C18, S4, and P3.

5. The apparatus of claim 1, wherein the vector signaling code for at least one sub-system is S4, and for at least one other sub-system is P3.

6. The apparatus of claim 1, wherein each of the data encoders maintains a history of at least one previous transmission interval to insure its transmit vector changes in each transmission interval.

7. The apparatus of claim 1 implemented with parallel instantiations of the data history pre-coder.

8. The apparatus of claim 1, further comprising:

two or more receiver sub-systems, each receiver sub-system comprising;

a receive circuit receiving physical receive signals on a receive sub-channel,

a data decoder, decoding the received signals representing a received codeword of a vector signaling code,

a data post-decoder, accepting the decoded received signals and producing received sub-system data, and,

a global decoder, accepting received sub-system data from each of the two or more receiver sub-systems to be reconstituted into a received version of a second set of input data.

9. The apparatus of claim 8 wherein timing of at least each receiver is derived from signal transitions within receive sub-channel.

10. The apparatus of claim 8, wherein the global decoder performs a complementary computation on the received sub-system data to obtain the received version of the second set of input data.

11. The apparatus of claim 8, wherein each of the data post-decoders maintains a history of at least one previous reception interval to accurately produce its received sub-system data from the decoded received signals.

12. The apparatus of claim 8, wherein the timing of at least one receiver sub-channel receiver is derived from received signal transitions produced by the pre-coding of the corresponding sub-channel transmit data.

13. The apparatus of claim 8, wherein the timing of the global decoder is obtained from the timing of at least one sub-channel receiver.

14. The apparatus of claim 8, wherein each of the data decoders maintains a history of at least one previous reception interval to accurately deliver data to the post-decoder.

15. The apparatus of claim 8 implemented with parallel instantiations of the post-decoder.

16. The apparatus of claim 8, further comprises a clock extraction circuit, wherein the clock extraction circuit comprises one or more implementations from the group consisting of:

analog hysteresis, decision feedback, digital decision feedback, offset comparators, analog XOR logic, per-codeword detector logic, and per-codeword flip-flops.

17. The apparatus of claim 16, wherein the outputs of the per-codeword flip-flops are combined together and passed through a delay line circuit.

18. The apparatus of claim 17, wherein the output of the delay line is used to clear the per-codeword flip-flops.

19. A method comprising:

processing input data to be distributed across two or more sub-channels, each sub-channel comprising a plurality of signal lines;

performing in parallel for each of the two or more sub-channels;

pre-encoding a portion of input data distributed to the respective sub-channel to produce sub-channel transmit data;

encoding the sub-channel transmit data into a codeword of a vector signaling code; and

,

driving physical signals representing the codeword on the communications sub-channel.

20. The method of claim 19, further comprising:

detecting signals on two or more receive sub-channels to produce received signals, each receive sub-channel comprising a plurality of signal lines;

deriving timing information for each of the two or more receive sub-channels from the respective sub-channel encoded codeword of the vector signaling code;

for each of the two or more communications sub-channels, decoding the received signals as a representation of a received codeword of the vector signaling code having M elements;

producing received sub-system data representing a reduce modulus (M−

1) data for each of the two or more receive sub-channels; and

,

processing received sub-system data from each of the two or more receive sub-channels to produce a received version of a second set of input data.