FSK decoding using envelope comparison in the digital domain

• US 9,363,119 B1
• Filed: 07/29/2015
• Issued: 06/07/2016
• Est. Priority Date: 07/29/2015
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Sathyanarayana, Aravind, Pai, Sandeep, Gudi, Balakrishna G., Kn, Dinesh Kumar
• Primary Examiner(s): Neff, Michael
• Application Number:
  US14/812,827
• Time in Patent Office: 314 Days
• Field of Search: 375/334
• US Class Current: 1/1
• CPC Class Codes: H03D 3/00 Demodulation of angle-, frequency- or phase- modulated oscillations H03D5/00, H03D9/00, H03D11/00 take precedence
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/152 using controlled oscillators, e.g. PLL arrangements
• CPC Class Codes: H04L 27/1563 using transition or level detection

Abstract

A method of FSK decoding includes generating a pulse waveform (R'"'"'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk). From R'"'"'Edge and Sys_clk clocks are generated including a first clock and second clock framing a logic ‘0’ level of the FSK signal, and a third clock and fourth clock framing a logic ‘1’ level of the FSK signal. At least four frequency envelopes are generated from the clocks including a logic ‘0’ envelope, a logic ‘1’ envelope, a lower frequency envelope below the logic ‘0’ envelope, and an upper frequency envelope above the logic ‘1’ envelope. R'"'"'Edge is compared to the four envelopes, and a decoded output is produced, logic ‘0’ if the R'"'"'Edge overlaps the logic ‘0’ envelope, logic ‘1’ if R'"'"'Edge overlaps the logic ‘1’ envelope, and a previous output state if R'"'"'Edge does not overlap the logic ‘0’ or logic ‘1’ envelope.

Claims

1. A method of frequency-shift keying (FSK) decoding, comprising:

generating a pulse waveform (R'"'"'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk);

generating a plurality of clocks from said R'"'"'Edge and said Sys_clk including a first clock and second clock framing a frequency for a logic ‘

0’

level of said FSK signal, and a third clock and fourth clock framing a frequency for a logic ‘

1’

level of said FSK signal;

generating at least four frequency envelopes from said plurality of clocks including a logic ‘

0’

envelope, a logic ‘

1’

envelope, a lower frequency envelope below said logic ‘

0’

envelope, and an upper frequency envelope above said logic ‘

1’

envelope;

comparing said R'"'"'Edge to said four frequency envelopes, and

outputting a decoded output of said logic ‘

0’

if said R'"'"'Edge overlaps said logic ‘

0’

envelope, said logic ‘

1’

if said R'"'"'Edge overlaps said logic ‘

1’

envelope, and a previous output state if said R'"'"'Edge does not overlap said logic ‘

0’

envelope or overlap said logic ‘

1’

envelope.

2. The method of claim 1, further comprising signal conditioning and signal shaping said FSK signal before said generating said R'"'"'Edge.

3. The method of claim 2, wherein a Schmitt trigger is used for said signal shaping including removing of noise.

4. The method of claim 1, wherein said FSK signal is a binary FSK signal.

5. The method of claim 1, wherein said FSK signal is a multiple frequency-shift keying (MFSK) signal.

6. The method of claim 1, wherein all steps in said method are performed in a digital domain.

7. The method of claim 6, wherein said method is realized by a processor having associated memory.

8. The method of claim 1, wherein said first clock and said second clock are at frequencies below a carrier frequency of said FSK signal, and wherein said third clock and said fourth clock are at frequencies above said carrier frequency of said FSK signal.

9. A frequency-shift keying (FSK) decoder, comprising:

a rising edge detector (RED) for generating a pulse waveform (R'"'"'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk);

a clock generator for generating a plurality of clocks from said R'"'"'Edge and said Sys_clk including a first clock and second clock framing a frequency for a logic ‘

0’

level of said FSK signal and a third clock and fourth clock framing a frequency for a logic ‘

1’

level of said FSK signal;

an envelope generator for generating at least four frequency envelopes from said plurality of clocks including a logic ‘

0’

envelope, a logic ‘

1’

envelope, a lower frequency envelope below said logic ‘

0’

envelope, and an upper frequency envelope above said logic ‘

1’

envelope, and

a comparator for comparing said R'"'"'Edge to said four frequency envelopes and providing a decoded output, said decoded output being said logic ‘

0’

if said R'"'"'Edge overlaps said logic ‘

0’

envelope, said logic ‘

1’

if said R'"'"'Edge overlaps said logic ‘

1’

envelope, and a previous output state if said R'"'"'Edge does not overlap said logic ‘

0’

envelope or overlap said logic ‘

1’

envelope.

10. The FSK decoder of claim 9, further comprising a Schmitt trigger and signal conditioning block (wave shaper) for signal conditioning and signal shaping said FSK signal before said generating said R'"'"'Edge.

11. The FSK decoder of claim 9, wherein said RED, said clock generator, said envelope generator and said comparator all comprise digital circuitry implemented by a processor having associated memory.

12. The FSK decoder of claim 9, wherein said RED outputs said R'"'"'Edge having a pulse width of said Sys_clk at every rising edge of said FSK signal.

13. The FSK decoder of claim 9, wherein said Sys_clk is further coupled to an input of said envelope generator and to an input of said comparator.

14. The FSK decoder of claim 9, wherein said FSK signal is a multiple frequency-shift keying (MFSK) signal and wherein said envelope generator is for generating 8 of said frequency envelopes from said plurality of clocks.

15. The FSK decoder of claim 9, wherein said first clock and said second clock are at frequencies below a carrier frequency of said FSK signal, and wherein said third clock and said fourth clock are at frequencies above said carrier frequency of said FSK signal.