Three-dimensional multilayer solenoid transformer

• US 9,363,902 B2
• Filed: 07/08/2014
• Issued: 06/07/2016
• Est. Priority Date: 05/03/2012
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Lo, Chi Shun, Kim, Jonghae, Zuo, Chengjie, Yun, Changhan Hobie
• Primary Examiner(s): Jiang, Lisha
• Application Number:
  US14/326,189
• Publication Number:
  US 20140322435A1
• Time in Patent Office: 700 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01F 2017/004 with the coil helically wound around an axis without a core
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H05K 3/465 by applying an insulating layer having channels for the next circuit layer

Abstract

This disclosure provides implementations of inductors, transformers, and related processes. In one aspect, a device includes a substrate having first and second surfaces. A first inducting arrangement includes a first set of vias, a second set of vias, a first set of traces arranged over the first surface connecting the first and second vias, and a second set of traces arranged over the second surface connecting the first and second vias. A second inducting arrangement is inductively-coupled and interleaved with the first inducting arrangement and includes a third set of vias, a fourth set of vias, a third set of traces arranged over the first surface connecting the third and fourth vias, and a fourth set of traces arranged over the second surface connecting the third and fourth vias. One or more sets of dielectric layers insulate portions of the traces from one another.

Claims

1. A method comprising:

providing a substrate having a first surface and a second surface opposite the first surface;

forming a plurality of vias in the substrate that each extend at least from the first surface to the second surface through the substrate;

plating or filling the plurality of vias with a conductive material to form a plurality of conductive vias, the plurality of conductive vias including a first set of vias, a second set of vias, a third set of vias, and a fourth set of vias;

depositing a first conductive layer over the first surface to form a first set of conductive traces over the first surface that each connect a via from the first set of vias with a via from the second set of vias;

depositing one or more first dielectric layers over portions of the first set of traces;

depositing a second conductive layer over the one or more first dielectric layers to form a second set of conductive traces that each connect a via from the third set of vias with a via from the fourth set of vias;

depositing a third conductive layer over the second surface to form a third set of conductive traces that each connect a via from the third set of vias with a via from the fourth set of vias;

depositing one or more second dielectric layers over portions of the third set of traces;

depositing a fourth conductive layer over the one or more second dielectric layers to form a fourth set of conductive traces that each connect a via from the first set of vias with a via from the second set of vias, wherein;

the first set of vias, the second set of vias, the first set of traces, and the fourth set of traces form a first conductive path of a first inducting arrangement, the first conductive path having a first axis of revolution;

the third set of vias, the fourth set of vias, the second set of traces, and the third set of traces form a second conductive path of a second inducting arrangement, the second conductive path having a second axis of revolution; and

the first axis of revolution is laterally offset from the second axis of revolution, at least part of the first axis of revolution being inside the second inducting arrangement, at least part of the second axis of revolution being inside the first inducting arrangement.

2. The method of claim 1, wherein an effective number of turns of the first conductive path and an effective number of turns of the second conductive path are substantially equal as a result of the lateral offset such that the first inducting arrangement is inductively-coupled with the second inducting arrangement with a transformation ratio of substantially 1:

1.

3. The method of claim 1, wherein magnetic field lines within the substrate within the region of the substrate within both the first and the second inducting arrangements are parallel with the first and the second surfaces.

4. The method of claim 1, wherein:

the first set of vias are arranged along a first row and the second set of vias are arranged along a second row; and

the third set of vias are arranged along a third row and the fourth set of vias are arranged along a fourth row.

5. The method of claim 4, wherein:

the first row is substantially parallel with the second row; and

the third row is substantially parallel with the fourth row.

6. The method of claim 5, wherein:

the first row is substantially parallel with the third row; and

the second row is substantially parallel with the fourth row.

7. The method of claim 1, wherein the substrate is formed from glass, sapphire, or quartz.