Optimizing power usage by factoring processor architectural events to PMU
First Claim
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1. A processor comprising:
- a plurality of cores, one or more of the plurality of cores including;
a plurality of thermal sensors to provide thermal data for the one or more of the plurality of cores; and
a plurality of counters each to count a number of occurrences of an architectural event;
a bus to communicate the thermal data and architectural event information, wherein the bus includes a plurality of branches including a first branch to monitor the plurality of counters of a first core in a first plurality of time slots and a second branch to monitor the plurality of thermal sensors of a second core in a second plurality of time slots; and
a power control unit coupled to the bus to modify a power state of one of the plurality of cores in response to an occurrence of an architectural event in the one of the plurality of cores.
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Abstract
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
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Citations
12 Claims
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1. A processor comprising:
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a plurality of cores, one or more of the plurality of cores including; a plurality of thermal sensors to provide thermal data for the one or more of the plurality of cores; and a plurality of counters each to count a number of occurrences of an architectural event; a bus to communicate the thermal data and architectural event information, wherein the bus includes a plurality of branches including a first branch to monitor the plurality of counters of a first core in a first plurality of time slots and a second branch to monitor the plurality of thermal sensors of a second core in a second plurality of time slots; and a power control unit coupled to the bus to modify a power state of one of the plurality of cores in response to an occurrence of an architectural event in the one of the plurality of cores. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification