Memory access requests in hybrid memory system

• US 9,367,247 B2
• Filed: 08/20/2013
• Issued: 06/14/2016
• Est. Priority Date: 08/20/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Venkata, Sumanth Jannyavula
• Primary Examiner(s): TSAI, SHENG JEN
• Application Number:
  US13/971,773
• Publication Number:
  US 20150058526A1
• Time in Patent Office: 1,029 Days
• Field of Search: 711/103, 711/154
• US Class Current: 1/1
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/068 Hybrid storage device

Abstract

Incoming memory access requests are routed in a set of incoming queues, the incoming memory access requests comprise a range of host logical block addresses (LBAs) that correspond to a memory space of a primary memory. The host LBA range is directly mapped to clusters of secondary memory, the secondary memory corresponding to a memory space of a secondary memory. Each incoming memory access request queued in the set of incoming queues is transformed into one or more outgoing memory access requests that include a range of secondary memory clusters or one or more clusters of secondary memory clusters. The outgoing memory access requests are routed in a set of outgoing queues. The secondary memory is accessed using the outgoing memory access requests.

Claims

1. A device, comprising:

a hybrid controller configured to manage data transfers between a host processor and a secondary memory, the secondary memory configured to serve as a cache for a primary memory, the primary memory including a memory space corresponding to host logical block addresses (LBAs), the hybrid controller configured to;

receive incoming memory access requests from the host processor, the memory access requests including a range of host LBAs;

route the incoming memory access requests to a set of incoming queues by implementing a priority scheme, comprising;

routing invalidate requests in an invalidate ready queue to an execute queue as a first priority, the execute queue including requests that are ready to be executed;

routing read requests in a read ready queue to the execute queue as a second priority; and

routing promotion requests in a promotion ready queue as a third priority;

map the range of host LBAs directly into clusters of the secondary memory;

transform each incoming memory access request into one or more outgoing memory access requests, each outgoing memory access request including a range or cluster of secondary memory;

route the outgoing memory access requests from the incoming queues into a set of outgoing queues; and

access the secondary memory using the outgoing memory access requests.

2. The device of claim 1, wherein the incoming memory access requests comprise:

read requests, each read request respectively including a host LBA range;

write requests, each write request respectively including a host LBA range that is aligned to secondary memory clusters; and

invalidate requests, each invalidate request respectively including a host LBA range that is aligned to secondary memory clusters.

3. The device of claim 2, wherein the incoming queues include one or more of:

a wait queue, each wait queue including requests that are waiting to be executed; and

an execute queue including requests that are ready to be executed.

4. The device of claim 3, wherein the wait queue includes requests that conflict with other requests.

5. The device of claim 2, wherein the set of incoming queues include:

an incoming free queue containing a number of incoming nodes; and

a wait queue, wherein an incoming node is removed from the incoming free queue when a memory access request is queued in the wait queue and the incoming node is returned to the incoming free queue after the memory access request is completed.

6. The device of claim 2, wherein the outgoing queues include one or more of:

a set of ready queues, each ready queue of the set of ready queues configured to queue memory access requests that are ready for execution.

7. The device of claim 6, wherein the set of outgoing queues comprises:

an outgoing free queue containing a number outgoing nodes;

one or more outgoing execute queues;

wherein an outgoing node is removed from the outgoing free queue when an outgoing memory access request is queued in one of the outgoing execute queues and the outgoing node is returned to the outgoing free queue after the memory access request is completed.

8. The device of claim 6, wherein the set of outgoing queues comprises an outgoing completed queue, the completed queue including requests that have been executed.

9. A method of operating a hybrid memory system that includes a primary memory and a secondary memory, the method comprising:

routing incoming memory access requests in a set of incoming queues according to a priority scheme, the incoming memory access requests comprising a range of host logical block addresses (LBAs) that correspond to a memory space of the primary memory the priority scheme, comprising;

routing invalidate requests in an invalidate ready queue to an execute queue as a first priority, the execute queue including requests that are ready to be executed;

routing read requests in a read ready queue to the execute queue as a second priority; and

routing promotion requests in a promotion ready queue as a third priority;

directly mapping the host LBA range to clusters of secondary memory, the clusters of secondary memory corresponding to a memory space of the secondary memory;

transforming each incoming memory access request queued in the set of incoming queues into one or more outgoing memory access requests, the outgoing memory comprising a range of secondary memory or one or more clusters of secondary memory;

routing the one or more outgoing memory access requests in a set of outgoing queues; and

accessing the secondary memory using the outgoing memory access requests.

10. The method of claim 9, wherein routing the incoming memory access requests comprises implementing a priority scheme for routing the memory access requests in the set of incoming queues.

11. The method of claim 10, wherein the priority scheme includes routing memory access requests that take a smaller amount of time to execute before routing memory access request that take a larger amount of time to execute.

12. The method of claim 10, wherein the priority scheme includes routing host memory access requests before routing memory access requests that do not originate in the host.

13. The method of claim 10, wherein the priority scheme includes routing garbage collection requests when there are no outstanding host initiated requests.

14. A controller system for a hybrid memory system, the controller comprising:

a hybrid controller configured to control data transfers between the host processor and a flash memory, the flash memory configured to serve as a cache for a magnetic disk, the hybrid controller comprising;

a flash content and transfer management (FCTM) layer configured to;

receive the incoming memory access requests from a higher layer of the hybrid controller;

route the incoming data access requests in a set of incoming queues by implementing a priority scheme, comprising;

routing invalidate requests in an invalidate ready queue to an execute queue as a first priority, the execute queue including requests that are ready to be executed;

routing read requests in a read ready queue to the execute queue as a second priority; and

routing promotion requests in a promotion ready queue as a third priority;

transform each of the memory access requests from the set of incoming queues into a plurality of outgoing memory access requests;

route the plurality of outgoing memory access requests in a set of outgoing queues; and

send the outgoing memory access requests to a lower layer of the hybrid controller.

15. The controller system of claim 14, wherein the incoming memory access requests comprise:

read requests, each read request respectively including a host LBA range;

write requests, each write request respectively including a host LBA range that is aligned to secondary memory clusters; and

invalidate requests, each invalidate request respectively including a host LBA range that is aligned to secondary memory clusters.

16. The controller system of claim 15, wherein the incoming queues include one or more of:

a free queue containing a number of incoming nodes;

a wait queue, each wait queue including requests that are waiting to be executed; and

an execute queue including requests that are ready to be executed.

17. The controller system of claim 16, wherein the FCTM layer is configured to remove an incoming node from an incoming free queue when a memory access request is queued in a wait queue and return the incoming node to the incoming free queue after the memory access request is completed.

18. The controller system of claim 15, wherein the outgoing queues include one or more of:

a set of ready queues, each ready queue of the set of ready queues configured to queue memory access requests that are ready for execution;

one or more outgoing execute queues;

a free queue containing a number outgoing nodes wherein the FCTM layer is configured to remove an outgoing node from the outgoing free queue when an outgoing memory access request is queued in one of the outgoing execute queues and return the outgoing node to the outgoing free queue after the memory access request is completed; and

the set of outgoing queues comprises an outgoing completed queue, the completed queue including requests that have been executed.