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Memory access requests in hybrid memory system

  • US 9,367,247 B2
  • Filed: 08/20/2013
  • Issued: 06/14/2016
  • Est. Priority Date: 08/20/2013
  • Status: Active Grant
First Claim
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1. A device, comprising:

  • a hybrid controller configured to manage data transfers between a host processor and a secondary memory, the secondary memory configured to serve as a cache for a primary memory, the primary memory including a memory space corresponding to host logical block addresses (LBAs), the hybrid controller configured to;

    receive incoming memory access requests from the host processor, the memory access requests including a range of host LBAs;

    route the incoming memory access requests to a set of incoming queues by implementing a priority scheme, comprising;

    routing invalidate requests in an invalidate ready queue to an execute queue as a first priority, the execute queue including requests that are ready to be executed;

    routing read requests in a read ready queue to the execute queue as a second priority; and

    routing promotion requests in a promotion ready queue as a third priority;

    map the range of host LBAs directly into clusters of the secondary memory;

    transform each incoming memory access request into one or more outgoing memory access requests, each outgoing memory access request including a range or cluster of secondary memory;

    route the outgoing memory access requests from the incoming queues into a set of outgoing queues; and

    access the secondary memory using the outgoing memory access requests.

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