Processor instruction set for controlling an event source to generate events used to schedule threads

• US 9,367,321 B2
• Filed: 03/14/2007
• Issued: 06/14/2016
• Est. Priority Date: 03/14/2007
• Status: Active Grant

• Current Assignee: XMOS Ltd.
• Original Assignee: XMOS Ltd.
• Inventors: May, Michael David
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): NIELSEN, KEITH A
• Application Number:
  US11/717,620
• Publication Number:
  US 20080229310A1
• Time in Patent Office: 3,380 Days
• Field of Search: 712/214, 712/228, 712/E9.032
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence

Abstract

The invention provides a processor comprising: an execution unit, and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread. The execution unit is configured to execute thread scheduling instructions which manage the runnable statuses. The thread scheduling instructions including at least: one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of the events upon which continued execution of the respective thread depends. The continued execution comprises retrieval of a continuation point vector for the respective thread.

Claims

1. A processor comprising:

an execution unit;

a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each respective thread, each thread represented in a respective one of a plurality of sets of thread registers; and

a plurality of event sources being hardware resources comprising one or more ports for transferring data between the processor and a device external to the processor, and/or one or more channels of an interconnect system for communicating between one of said plurality of sets of thread registers representing one of said plurality of threads and another set of thread registers representing another thread;

wherein the execution unit is configured to execute thread scheduling instructions being instructions of an instruction set of the execution unit which manage said runnable statuses;

wherein the thread scheduling instructions of the instruction set include a source event enable instruction, the execution unit being configured to be operated by an opcode of the event enable instruction to send a signal to a specified one of said ports or channels via a direct hardwired connection between the execution unit and the specified port or channel in order to set the specified port or channel to a mode in which it generates a respective event dependent on activity occurring at the specified port or channel, the direct hardwired connection being a connection not via a bus;

wherein each of said ports or channels is operable to be associated with one of the plurality of threads and with a specified one of a plurality of different potential code locations; and

wherein the thread scheduling instructions also include a wait instruction which sets one of said runnable statuses to suspend the respective thread until an associated one of said ports or channels generates its respective event, such that execution of the respective thread continues from the specified one of the plurality of different potential code locations.

2. The processor according to claim 1, wherein the thread scheduling instructions include a source event disable instruction, the execution unit being configured to be operated by an opcode of the event enable instruction to send a signal from the execution unit to the specified port or channel via said direct hardwired connection in order to set the specified port or channel to a mode in which it does not generate the respective event.

3. The processor according to claim 1, wherein the thread scheduling instructions include:

a thread event enable instruction which sets a control status of a thread to event-enabled to allow the event-enabled thread to accept events, and a thread event disable instruction which sets a control status of a thread to event-disabled to stop the event-disabled thread from accepting events.

4. The processor according to claim 3, wherein each of said sets of thread registers comprises a register for storing said control status.

5. The processor according to claim 3, wherein the execution unit is arranged to execute said thread event enable instruction and subsequently execute a plurality of said source event enable instructions each for a respective port or channel.

6. The processor according to claim 1, wherein the execution unit is configured to execute one or more additional instructions each of which configures a parameter associated with a specified one of said ports or channels wherein each of said ports or channels comprises one or more registers for storing the parameter being configured by each of said one or more additional instructions.

7. The processor according to claim 6, wherein the one or more additional instructions include at least a set condition instruction which sets a condition upon which a specified one of said ports or channels generates the respective event.

8. The processor according to claim 7, wherein the one or more additional instructions include a set data instruction which provides data associated with the condition.

9. The processor according of claim 6, wherein the one or more additional instructions include at least a set vector instruction which sets a continuation point vector specifying said one of the plurality of potential code locations associated with the specified event source.

10. The processor according to claim 1, wherein the thread scheduling instructions further include an interrupt enable instruction which sets a control status of a thread to interrupt-enabled to allow the interrupt-enabled thread to accept interrupts, and an interrupt disable instruction which sets a control status of a thread to interrupt-disabled to stop the interrupt-disabled thread from accepting interrupts.

11. The processor according to claim 1, wherein the thread scheduling instructions further include:

an input instruction which pauses a thread pending input of data from one of said ports or channels, and an output instruction which pauses a thread pending the availability of one of said ports or channels for outputting data;

wherein continued execution of a thread paused by said input and output instructions resumes where execution was paused.

12. The processor according to claim 11, wherein the processor is arranged to execute a first one of said source event enable instructions to enable a first port or channel to generate a first event dependent on a first activity occurring at the first port or channel, to execute at least one of said additional instructions to configure one or more parameters for the first port or channel, to execute said wait instruction to suspend the respective thread pending the first activity, to disable the first port or channel from generating the first event after occurrence of the first activity, to leave the one or more parameters configured for the first port or channel after said disabling of the first port or channel, and to re-use said one or more parameters by executing a second of said source event enable instructions to enable the first port or channel to generate a further instance of the first event dependent on a further occurrence of the first activity at the first port or channel.

13. The processor according to claim 12, wherein the processor is arranged to execute at least one of said input and output instructions between said execution of said wait instruction and said execution of said second event source enable instruction.

14. The processor according to claim 1, wherein the thread scheduling instructions include a clear instruction to disable all events for a thread.

15. The processor according to claim 1, wherein the port or channel specified by at least one of the one or more source event enable instructions comprises the channel, such that said activity comprises activity occurring over the channel.

16. The processor according to claim 1, wherein the port or channel specified by at least one of the one or more source event enable instructions comprises the port, such that said activity comprises activity occurring at the port.

17. The processor according to claim 1, wherein the execution unit is adapted to execute a plurality of said source event enable instructions each of which sets a respective port or channel to a mode in which it generates an event dependent on activity occurring at that port or channel, and said wait instruction sets said one of the runnable statuses to suspend the respective thread until generation of an event from any of the respective ports or channels.

18. The processor according to claim 1, wherein said wait instruction can be either a wait enable true instruction which waits only if its condition operand is true, or a wait enable false instruction which waits only if its condition operand is false.

19. The processor according to claim 1, wherein said source event enable instruction can be either a source event enable true instruction which enables the specified port or channel to generate events if an operand is true and disables it otherwise, or a source event enable false instruction which enables the specified port or channel to generate events if an operand is false and disables it otherwise.

20. The processor according to claim 1, wherein the processor is adapted to automatically disable a thread from accepting events upon occurrence of the respective event without executing a thread event disable instruction.

21. The processor according to claim 1, wherein the processor is adapted to automatically disable the port or channel from generating events upon occurrence of a respective event without executing a source event disable instruction.

22. The processor according to claim 1, wherein the processor is adapted to complete the wait instruction and continue the respective thread immediately if the respective event is generated on or before execution of the wait instruction.

23. The processor of claim 1, wherein said device external to the processor is an off-chip device on another chip than said processor.

24. The processor of claim 1, wherein said device external to the processor comprises another processor.

25. The processor of claim 1, wherein the association of ports or channels with one of the plurality of threads comprises storing a thread identifier in a thread identifier register of the port or channel.

26. A method of controlling a thread scheduler to schedule a plurality of threads for execution by an execution unit within a processor, each thread represented in a respective one of a plurality of sets of thread registers;

and the processor comprising a plurality of event sources being hardware resources comprising one or more ports for transferring data between the processor and a device external to the processor, and/or one or more channels of an interconnect system for communicating between one of said plurality of sets of thread registers representing one of said plurality of threads and another set of thread registers representing another thread; and

the method comprising;

scheduling the plurality of threads in dependence on a respective status for each respective thread; and

operating the execution unit to execute thread scheduling instructions being instructions of an instruction set of the execution unit for managing statuses of threads;

wherein said thread scheduling instructions include a source event enable instruction having an opcode which operates the execution unit to send a signal to a specified one of said ports or channels via a direct hardwired connection between the execution unit and the specified port or channel in order to set the specified port or channel to a mode in which it generates a respective event dependent on activity occurring at the specified port or channel, the direct hardwired connection being a connection not via a bus;

wherein each of said ports or channels is operable to be associated with one of said threads and with a specified one of a plurality of different potential code locations; and

wherein the thread scheduling instructions also include a wait instruction which sets one of said runnable statuses to suspend the respective thread until an associated one of said ports or channels generates its respective event, such that execution of the respective thread continues from the specified one of the plurality of different potential code locations.

27. The method according to claim 26, wherein the thread scheduling instructions include a source event disable instruction having an opcode which operates the execution unit to send a signal to the specified port or channel via said direct hardwired connection in order to set the specified port or channel to a mode in which it does not generate the respective event.

28. The method according to claim 26, wherein the thread scheduling instructions include:

a thread event enable instruction which sets a control status for a thread to event-enabled to allow the event-enabled thread to accept events, and a thread event disable instruction which sets a control status of a thread to event-disabled to stop the event-disabled thread from accepting events.

29. The method according to claim 28, comprising storing said control status in at least one register of each of said sets of thread registers.

30. The method according to claim 28, comprising executing said thread event enable instruction and subsequently executing a plurality of said source event enable instructions each for a respective source.

31. The method according to claim 26, further comprising executing one or more additional instructions each of which configures a parameter associated with a specified one of said ports or channels, and storing, in one or more registers of the specified port or channel, the parameter being configured by each of the one or more additional instructions.

32. The method according to claim 31, wherein said one or more additional instructions include at least a set condition instruction which sets a condition upon which a specified one of said ports or channels generates the respective event.

33. The method according to claim 32, wherein said one or more additional instructions include a set data instruction which provides data associated with the condition.

34. The method according to claim 31, wherein said one or more additional instructions include at least a set vector instruction which sets a continuation point vector specifying said one of the plurality of different potential code locations associated with the specified port or channel.

35. The method according to claim 26, wherein the thread scheduling instructions further include:

an interrupt enable instruction which sets a control status for a thread to interrupt-enabled to allow the interrupt-enabled thread to accept interrupts, and an interrupt disable instruction which sets a control status for a thread to interrupt-disabled to stop the interrupt-disabled thread from accepting interrupts.

36. The method according to claim 26, wherein the thread scheduling instructions further include:

an input instruction which pauses a thread pending input of data from one of said ports or channels, and an output instruction which pauses a thread pending the availability of one of said ports or channels for outputting data;

wherein continued execution of a thread paused by said input and output instructions resumes where execution was paused.

37. The method according to claim 36, comprising:

executing a first one of said source event enable instructions to enable a first port or channel to generate a first event dependent on a first activity occurring at the first port or channel,

executing at least one of said additional instructions to configure one or more parameters for the first event source,

executing said wait instruction to suspend the respective thread pending the first activity,

disabling the first port or channel from generating the first event source after occurrence of the first activity,

leaving said one or more parameters configured for the first port or channel after said disabling of the first port or channel, and

re-using said parameters by executing a second of said source event enable instructions to enable the first port or channel to generate a further instance of the first event dependent on a further occurrence of the first activity at the first port or channel.

38. The method according to claim 37, comprising executing at least one of said input and output instructions between said execution of said wait instruction and said execution of said second event source enable instruction.

39. The method according to claim 26, wherein said thread scheduling instructions include a clear instruction to disable all events for a thread.

40. The method according to claim 26, wherein the port or channel specified by at least one of the one or more source event enable instructions comprises the channel, such that said activity comprises activity occurring over the channel.

41. The method according to claim 26, wherein the port or channel specified by at least one of the one or more source event enable instructions comprises the port, such that said activity comprises activity occurring at the port.

42. The method according to claim 26, comprising:

executing a plurality of said source event enable instructions to set each of a plurality of respective ports or channels to a mode in which it generates an event dependent on activity occurring at that port or channel, and

executing said wait instruction to set said one of the runnable statuses to suspend the respective thread until generation of an event from any of the respective ports or channels.

43. The method according to claim 26, wherein said wait instruction can be either a wait enable true instruction which waits only if its condition operand is true, or a wait enable false instruction which waits only if its condition operand is false.

44. The method according to claim 26, wherein said source event enable instruction can be either a source event enable true instruction which enables the specified port or channel to generate events if an operand is true and disables it otherwise, or a source event enable false instruction which enables the specified port or channel source to generate events if an operand is false and disables it otherwise.

45. The method according to claim 26, comprising automatically disabling a thread from accepting events upon occurrence of the respective event without executing a thread event disable instruction.

46. The method according to claim 26, comprising automatically disabling the event source from generating events upon occurrence of a respective event without executing a source event disable instruction.

47. The method according to claim 26, comprising completing the wait instruction and continuing the respective thread immediately if the respective event is generated on or before execution of the wait instruction.

48. A processor comprising:

an execution unit;

a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread; and

a plurality of event sources for generating events;

wherein the execution unit is configured to execute thread scheduling instructions which manage said runnable statuses, the thread scheduling instructions including one or more source event enable instructions each of which sets a specified one of said event sources to a mode in which it generates one of said events dependent on activity occurring at the specified source, and a wait instruction which sets one of said runnable statuses to suspend the respective thread until generation of one of said events upon which continued execution of that thread depends;

wherein a continuation point vector for the respective thread is associated with the specified event source, and, if suspended by said wait instruction, said continued execution comprises retrieving the continuation point vector for the respective thread and continuing execution from the continuation point vector; and

wherein the thread scheduling instructions further include an input instruction which pauses a thread pending input of data from an event source, and an output instruction which pauses a thread pending the availability of an event source for outputting data, wherein continued execution of a thread does not involve retrieval of a continuation point vector for that thread if paused by said input and output instructions instead of the wait instruction.