Processor assist facility

• US 9,367,323 B2
• Filed: 06/15/2012
• Issued: 06/14/2016
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Greiner, Dan F., Jacobi, Christian, Philley, Randall W., Relson, Peter J., Slegel, Timothy J.
• Primary Examiner(s): Partridge, William B
• Assistant Examiner(s): Nguyen, William
• Application Number:
  US13/524,871
• Publication Number:
  US 20130339687A1
• Time in Patent Office: 1,460 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/466 Transaction processing

Abstract

An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.

Claims

1. A computer program product for controlling execution within a computing environment, the computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

detecting, by a processor, that execution of an instruction stream has aborted;

based on detecting that execution of the instruction stream has aborted and prior to retrying execution of the instruction stream, initiating execution of a machine instruction to indicate to the processor that re-execution of the instruction stream is a retry, the machine instruction being defined for computer execution according to a computer architecture and comprising a field to specify a requested assist operation to be performed by the processor, a value of the field indicating that re-execution of the instruction stream is a retry and indicating to the processor that an action is to be taken to facilitate successful re-execution of the instruction stream;

based on initiating execution of the machine instruction, performing the action; and

retrying execution of the instruction stream.

2. The computer program product of claim 1, wherein the machine instruction is a perform processor assist instruction that further includes an operation code to specify a perform processor assist operation, and wherein the field is separate from the operation code and specifies an abort assist operation.

3. The computer program product of claim 1, wherein the field comprises an operation code specifying an abort assist operation.

4. The computer program product of claim 1, wherein the instruction stream is a transaction, the transaction effectively delaying committing transactional stores to main memory until completion of a selected transaction.

5. The computer program product of claim 4, wherein the machine instruction further comprises a register field, the register field identifying a register usable by a program to indicate a number of times the transaction has aborted, and wherein the initiating execution comprises providing the number of times to the processor, the processor to take action based on the number of times the transaction has aborted.

6. The computer program product of claim 5, wherein the method further comprises:

based on execution of the machine instruction and a value of the identified register, determining by the processor one or more actions to facilitate successful re-execution of the transaction; and

re-executing the transaction.

7. The computer program product of claim 6, wherein the performing one or more actions comprises setting state of the processor.

8. The computer program product of claim 1, wherein the instruction stream is a transaction, and wherein the method further comprises:

initiating the transaction via a transaction begin instruction; and

detecting an abort of the transaction.

9. The computer program product of claim 8, wherein the method further comprises re-executing the transaction, subsequent to execution of the machine instruction.

10. The computer program product of claim 1, wherein the machine instruction further comprises another field, the another field identifying a register usable by a program to indicate a count of a number of times the instruction stream has aborted, and wherein the initiating execution of the machine instruction includes providing the number of times to the processor, the processor to take action based on the number of times the instruction stream has aborted, wherein different actions are taken based on the number of times the instruction stream has aborted to enable successful re-execution of the aborted instruction stream.

11. The computer program product of claim 1, wherein the action comprises at least one of:

performing random delays within the processor;

delaying processing within the processor based on a number of times the instruction stream has aborted as indicated by the machine instruction;

temporarily suspending out-of-order execution within the processor;

or disabling branching.

12. The computer program product of claim 1, wherein the action to be taken is to restrict processing of the processor or another processor during the retry, the action to be performed being selected based on an abort count associated with the instruction stream, wherein there are a plurality of abort counts configured that have selectable actions associated therewith at different levels of restrictiveness, and wherein the abort count associated with the instruction stream is an abort count of the plurality of abort counts.

13. The computer program product of claim 1, wherein the action to be performed is selected based on an abort count associated with the instruction stream, wherein a range of abort counts has one or more selectable actions associated therewith, and wherein the action selected to be performed comprises one or more actions of the one or more selectable actions associated with the range of abort counts comprising the abort count.

14. A computer system for controlling execution within a computing environment, the computer system comprising:

a memory; and

a processor having one or more hardware components, the processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising;

detecting, by the processor, that execution of an instruction stream has aborted;

based on detecting that execution of the instruction stream has aborted and prior to retrying execution of the instruction stream, initiating execution of a machine instruction to indicate to the processor that re-execution of the instruction stream is a retry, the machine instruction being defined for computer execution according to a computer architecture and comprising a field to specify a requested assist operation to be performed by the processor, a value of the field indicating that re-execution of the instruction stream is a retry and indicating to the processor that an action is to be taken to facilitate successful re-execution of the instruction stream;

based on initiating execution of the machine instruction, performing the action; and

retrying execution of the instruction stream.

15. The computer system of claim 14, wherein the machine instruction is a perform processor assist instruction that further includes an operation code to specify a perform processor assist operation, and wherein the field is separate from the operation code and specifies an abort assist operation.

16. The computer system of claim 14, wherein the field comprises an operation code specifying an abort assist operation.

17. The computer system of claim 14, wherein the instruction stream is a transaction, the transaction effectively delaying committing transactional stores to main memory until completion of a selected transaction, and wherein the machine instruction further comprises a register field, the register field identifying a register usable by a program to indicate a number of times the transaction has aborted, and wherein the initiating execution comprises providing the number of times to the processor, the processor to take action based on the number of times the transaction has aborted.

18. The computer system of claim 17, wherein the method further comprises:

based on execution of the machine instruction and a value of the identified register, determining by the processor one or more actions to facilitate successful re-execution of the transaction; and

re-executing the transaction.

19. The computer system of claim 14, wherein the instruction stream is a transaction, and wherein the method further comprises:

initiating the transaction via a transaction begin instruction; and

detecting an abort of the transaction.

20. The computer system of claim 14, wherein the machine instruction further comprises another field, the another field identifying a register usable by a program to indicate a count of a number of times the instruction stream has aborted, and wherein the initiating execution of the machine instruction includes providing the number of times to the processor, the processor to take action based on the number of times the instruction stream has aborted, wherein different actions are taken based on the number of times the instruction stream has aborted to enable successful re-execution of the aborted instruction stream.