Reversible connector for accessory devices

• US 9,367,490 B2
• Filed: 06/13/2014
• Issued: 06/14/2016
• Est. Priority Date: 06/13/2014
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Huang, Heng, He, Yi, Evans, Duane Martin, Obie, Gene Robert
• Primary Examiner(s): Martinez, David E
• Application Number:
  US14/304,174
• Publication Number:
  US 20150363339A1
• Time in Patent Office: 732 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/10 Program control for peripheral devices G06F13/14 - G06F13/42 take precedence
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 21/33 using certificates

Abstract

Reversible connectors for accessory devices are described. In one or more implementations, a connector cable for an accessory of a host computing device is configured such that a head of the connector cable may be plugged into a corresponding port of the host in either orientation (straight or reverse). The host computing device is configured to sample signals associated with allocated pins of the connector to detect connection of the connector to an accessory port and to ascertain an orientation of the connector. A combination of high and low values of signals conveyed via these allocated pins upon insertion of the connector may be used by a controller of the host to distinguish between different types of devices and to resolve the orientation of the connector cable. A switching mechanism of the host computing device may then be configured to automatically route signals accordingly.

Claims

1. A method implemented by a host computing device comprising:

detecting connection of a connector to an accessory port of the host computing device based on signals conveyed via a pair of detection pins allocated in the connector;

ascertaining an orientation of the connection of the connector to the accessory port based on the signals, the signals indicating a logic state combination for the pair of detection pins, the logic state combination indicating whether an accessory device connected via the connector is a one wire device or a two wire device; and

configuring a switching mechanism of the host computing device to route signals according to the ascertained orientation and the logic state combination.

2. A method as described in claim 1, wherein detecting connection of the connector comprises sampling the signals conveyed via the pair of detection pins together and combining values that are obtained via the pair of detection pins to derive the logic state combination.

3. A method as described in claim 2, wherein sampling the signals conveyed via the pair of detection pins together comprises sampling the signals in parallel.

4. A method as described in claim 1, wherein the pair of detection pins form an interface to support hot plug detection and communications for device authentication, power exchange, and signal routing control.

5. A method as described in claim 4, wherein the interface is configurable based on a device type of the accessory device connected and the orientation of the connection to switch between different signal routing options and communication techniques.

6. A method as described in claim 1, wherein configuring the switching mechanism comprises directing positions for switches and multiplexers of the host computing device to produce straight or reversed signal paths according to the ascertained orientation.

7. A method as described in claim 6, wherein configuring the switching mechanism further comprises sending commands to the accessory device to cause set-up of signal routing via signal switching components of the accessory device under the direction of the host computing device.

8. A method as described in claim 1, wherein ascertaining an orientation of the connection of the connector comprises:

sampling signals associated with allocated detection pins of the connector to determine a device type for the accessory device as a one wire device or a two wire device; and

when the device type is a one wire device, determining the orientation of the connection directly from the sampled signals;

or

when the device type is a two wire device, resolving the orientation through an authentication sequence in which credentials supplied by the accessory device are employed to establish validity states for the detection pins indicative of the orientation.

9. A method as described in claim 8, wherein the credentials supplied by the accessory device comprise one or more resistor values exposed on one or more detection lines formed via the detection pins.

10. A host computing device comprising:

one or more microcontrollers;

an accessory port connectable to a connector for an accessory device;

one or more computer-readable storage media storing instructions that when executed via the one or more microcontrollers cause the host computing device to perform operations including;

detecting insertion of the connector into the accessory port via a pair of detection pins integrated with the connector;

obtaining a logic state combination of high and low logic states conveyed via the pair of detection pins;

determining a device type for the accessory device as a one wire device or a two wire device based upon the logic state combination;

ascertaining an orientation of the connector inserted in the accessory port including;

when the device type is a one wire device, determining the orientation of the connection directly from the logic state combination;

or

when the device type is a two wire device, sampling resistor values for one or more identity resistors of the accessory device via the pair of detection pins to establish validity states indicative of the orientation; and

setting-up signal routing according to the type of device and ascertained orientation.

11. A host computing device as described in claim 10, wherein a one wire device is a device that communicates via RX/TX that is combined on a single line and a two wire device is a device that communicates using separate RX and TX lines.

12. A host computing device as described in claim 10, wherein setting-up signal routing according to the type of device and ascertained orientation includes configuring a switching mechanism to route signals in straight or reversed signal paths according to the ascertained orientation.

13. A host computing device as described in claim 10, wherein determining the device type based upon the logic state combination comprises referencing a mapping of possible logic state combinations to detection cases to identify the device type.

14. A host computing device as described in claim 10, wherein the instructions further cause the host computing device to sample credentials supplied by the accessory device to determine whether the accessory device is an authorized device authorized for interaction with the host computing device or an unsupported device with which interaction is restricted.

15. A host computing device as described in claim 10, wherein the instructions are implemented via firmware corresponding to the one or more microcontrollers of the host computing device and the one or more microcontrollers are configured to operate independently of a primary processing system of the host computing device.

16. A host computing device comprising:

a processing system; and

one or more computer-readable storage media storing instructions that when executed via the processing system cause the host computing device to implement a security module that is configured to;

detect connection of a connector for an accessory device to an accessory port of the host computing device based on a logic state combination obtained via a pair of detection pins integrated with the connector, the connector and accessory port configured to support reversible connection of the connector to the accessory port;

identify a device type of the accessory device according to the logic state combination, the logic state combination indicating whether the accessory device is a one wire device or a two wire device;

ascertain an orientation of the connection of the connector to the accessory port; and

configure a switching mechanism of the host computing device to automatically route signals according to the identified device type and the ascertained orientation.

17. A host computing system as recited in claim 16, wherein the pair of detection pins form an interface to support hot plug detection and communications for device authentication, power exchange, and signal routing control.

18. A host computing system as recited in claim 16, wherein the switching mechanism is configured based on:

positions being set for switches and multiplexers of the host computing device to produce straight or reversed signal paths according to the ascertained orientation; and

commands being sent to the accessory device to cause set-up of signal routing on the accessory side via signal switching components of the accessory device under the direction of the host computing device.

19. A host computing system as recited in claim 16, wherein the logic state combination includes high and low logic states conveyed via the pair of detection pins.

20. A host computing system as recited in claim 16, wherein the orientation of the connection of the connector to the accessory port is ascertained based on:

a determination of the orientation directly from the logic state combination when the device type is a one wire device;

or

an authentication sequence in which credentials supplied by the accessory device are employed to establish validity states for the detection pins indicative of the orientation when the device type is a two wire device.