Reconfigurably designating master core for conditional output on sideband communication wires distinct from system bus

• US 9,367,497 B2
• Filed: 10/24/2014
• Issued: 06/14/2016
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Stephan
• Primary Examiner(s): KIM, KENNETH S
• Application Number:
  US14/522,931
• Publication Number:
  US 20150046680A1
• Time in Patent Office: 599 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 11/1423 by reconfiguration of paths
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 15/163 Interprocessor communication
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.

Claims

1. A method for dynamically reconfiguring a hierarchical relationship between one or more cores of a multi-core microprocessor comprising a system bus connected to a chipset, a plurality of cores, and sideband communication wires that are distinct from the system bus, the sideband communication wires facilitating non-system-bus inter-core communications, wherein at least some of the cores are operable to be reconfigurably designated as a master core, the method comprising:

determining an initial hierarchical configuration of the cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core; and

reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from the at least one core initially so designated, and assigns a master designation to a core not initially so designated;

wherein each core is configured to conditionally drive an output on a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.

2. The method of claim 1, further comprising generating the initial configuration by selectively blowing applicable fuses in each of the cores, wherein the applicable fuses define whether the core has, by default, one or more master credentials.

3. The method of claim 2, further comprising determining the initial configuration with use of configuration discovery microcode running on each of the cores.

4. The method of claim 1, wherein the modified configuration is provided by a system software program executed by the microprocessor.

5. The method of claim 4, further comprising a user designating the modified configuration through a user interface.

6. The method of claim 1, further comprising storing the modified configuration within the core.

7. The method of claim 6, further comprising coordinating power state management between the cores in accordance with the modified configuration.

8. The method of claim 1, wherein:

the multi-core microprocessor comprises a plurality of multi-core dies;

each multi-core die has a designated master core;

a set of inter-die sideband communication wires is provided between dies of the multi-core microprocessor;

each core of each die is connected to the set of inter-die sideband communication wires, and is conditionally enabled to drive an output on that set based upon its designation, or lack thereof, as the master core of the die; and

any core of each die is operable to be reconfigured to designate it, or remove its designation, if any, as the master of its die.

9. The method of claim 1, further comprising reconfiguring the cores according to a provisional configuration, wherein the provisional configuration:

designates a non-master core as a provisional master core;

disables the designated master core from driving an applicable sideband communication wire; and

enables the provisional master core to drive the applicable sideband communication wire.

10. The method of claim 9, further comprising:

a non-master core implementing a provisional configuration in response to detecting a condition consistent with disablement, inoperability, a fault, or a failure of the designated master core;

the non-master core distributing the provisional configuration to other cores affected by the provisional configuration; and

the non-master core conditionally repealing the provisional configuration if the designated master core, through a subsequent transaction, initiates a transfer of control back to itself.

11. A multi-core microprocessor, comprising:

a plurality of cores;

a system bus connected to a chipset; and

sideband communication wires that are distinct from the system bus that facilitate non-system-bus inter-core communications;

wherein at least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of configuring which core has primary responsibility for sideband-based inter-core communications;

wherein at least some of the cores are operable to determine an initial hierarchical configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as the master core;

wherein at least some of the cores are operable to reconfigure the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated; and

wherein each core is configured to conditionally drive an output on a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.

12. The multi-core microprocessor of claim 11, wherein the initial configuration is generated by selectively blowing applicable fuses in each of the cores, wherein the applicable fuses define whether the core has, by default, one or more master credentials.

13. The multi-core microprocessor of claim 12, wherein the initial configuration is determined with use of configuration discovery microcode running on each of the cores.

14. The multi-core microprocessor of claim 11, wherein the modified configuration is provided by a system software program executable by the microprocessor.

15. The multi-core microprocessor of claim 14, wherein the modified configuration is designated by a user through a user interface.

16. The multi-core microprocessor of claim 11, wherein the modified configuration is stored within the core.

17. The multi-core microprocessor of claim 16, wherein power state management is coordinated between the cores in accordance with the modified configuration.

18. The multi-core microprocessor of claim 11, wherein:

the multi-core microprocessor comprises a plurality of multi-core dies;

each multi-core die has a designated master core;

a set of inter-die sideband communication wires is provided between dies of the multi-core microprocessor;

each core of each die is connected to the set of inter-die sideband communication wires, and is conditionally enabled to drive an output on that set based upon its designation, or lack thereof, as the master core of the die; and

any core of each die is operable to be reconfigured to designate it, or remove its designation, if any, as the master of its die.

19. The multi-core microprocessor of claim 11, wherein the cores are reconfigured according to a provisional configuration, wherein the provisional configuration:

designates a non-master core as a provisional master core;

disables the designated master core from driving an applicable sideband communication wire; and

enables the provisional master core to drive the applicable sideband communication wire.

20. The multi-core microprocessor of claim 18, wherein:

a non-master core implements a provisional configuration in response to detecting a condition consistent with disablement, inoperability, a fault, or a failure of the designated master core;

the non-master core distributes the provisional configuration to other cores affected by the provisional configuration; and

the non-master core conditionally repeals the provisional configuration if the designated master core, through a subsequent transaction, initiates a transfer of control back to itself.

21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a multi-core microprocessor, the computer usable program code comprising;

first program code for specifying a plurality of cores;

second program code for specifying a system bus connected to a chipset; and

third program code for specifying sideband communication wires that are distinct from the system bus that facilitate non-system-bus inter-core communications;

wherein at least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of configuring which core has primary responsibility for sideband-based inter-core communications;

wherein at least some of the cores are operable to determine an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core;

wherein at least some of the cores are operable to reconfigure the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated; and

wherein each core is configured to conditionally drive an output on a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.