Reconfigurably designating master core for conditional output on sideband communication wires distinct from system bus
First Claim
1. A method for dynamically reconfiguring a hierarchical relationship between one or more cores of a multi-core microprocessor comprising a system bus connected to a chipset, a plurality of cores, and sideband communication wires that are distinct from the system bus, the sideband communication wires facilitating non-system-bus inter-core communications, wherein at least some of the cores are operable to be reconfigurably designated as a master core, the method comprising:
- determining an initial hierarchical configuration of the cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core; and
reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from the at least one core initially so designated, and assigns a master designation to a core not initially so designated;
wherein each core is configured to conditionally drive an output on a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.
1 Assignment
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Accused Products
Abstract
A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.
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Citations
21 Claims
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1. A method for dynamically reconfiguring a hierarchical relationship between one or more cores of a multi-core microprocessor comprising a system bus connected to a chipset, a plurality of cores, and sideband communication wires that are distinct from the system bus, the sideband communication wires facilitating non-system-bus inter-core communications, wherein at least some of the cores are operable to be reconfigurably designated as a master core, the method comprising:
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determining an initial hierarchical configuration of the cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core; and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from the at least one core initially so designated, and assigns a master designation to a core not initially so designated; wherein each core is configured to conditionally drive an output on a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A multi-core microprocessor, comprising:
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a plurality of cores; a system bus connected to a chipset; and sideband communication wires that are distinct from the system bus that facilitate non-system-bus inter-core communications; wherein at least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of configuring which core has primary responsibility for sideband-based inter-core communications; wherein at least some of the cores are operable to determine an initial hierarchical configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as the master core; wherein at least some of the cores are operable to reconfigure the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated; and wherein each core is configured to conditionally drive an output on a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:
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computer usable program code embodied in said medium, for specifying a multi-core microprocessor, the computer usable program code comprising; first program code for specifying a plurality of cores; second program code for specifying a system bus connected to a chipset; and third program code for specifying sideband communication wires that are distinct from the system bus that facilitate non-system-bus inter-core communications; wherein at least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of configuring which core has primary responsibility for sideband-based inter-core communications; wherein at least some of the cores are operable to determine an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core; wherein at least some of the cores are operable to reconfigure the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated; and wherein each core is configured to conditionally drive an output on a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.
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Specification