Variation modeling

• US 9,367,654 B2
• Filed: 09/07/2015
• Issued: 06/14/2016
• Est. Priority Date: 02/28/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Chi-Wen, Lee, Hui Yu, Kuan, Jui-Feng, Cheng, Yi-Kan, Wen, Chin-Hua, Chou, Wen-Shen
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US14/846,975
• Publication Number:
  US 20150379174A1
• Time in Patent Office: 281 Days
• Field of Search: 320106-107, 320110-111
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2111/10 Numerical modelling
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method for back-end-of-line variation modeling is provided. A bounding box is defined within a design layout. A back-end-of-line variation parameter is determined for the bounding box. The back-end-of-line variation parameter is applied as a constraint for simulation of the design layout.

Claims

1. A method for back-end-of-line variation modeling, comprising:

defining a bounding box for a device within a design layout of a semiconductor arrangement, wherein a size of the bounding box is a function of patterns surrounding the device;

determining a back-end-of-line variation parameter for the bounding box;

applying, using a computing device, the back-end-of-line variation parameter as a back-end-of-line constraint for simulation of the design layout; and

modifying a physical feature of the design layout based upon a result of the simulation, wherein the design layout is implemented in fabrication of the device.

2. The method of claim 1, the determining a back-end-of-line variation parameter comprising:

deriving the back-end-of-line variation parameter based upon at least one of a back-end-of-line layer property or a back-end-of-line density.

3. The method of claim 1, comprising:

modifying a circuit design based upon the result of the simulation.

4. The method of claim 1, the determining a back-end-of-line variation parameter comprising:

deriving the back-end-of-line variation parameter based upon a back-end-of-line color property.

5. The method of claim 1, the determining a back-end-of-line variation parameter comprising:

deriving the back-end-of-line variation parameter based upon a back-end-of-line corner.

6. The method of claim 1, the determining a back-end-of-line variation parameter comprising:

deriving the back-end-of-line variation parameter based upon a horizontal direction property corresponding to a horizontal distance from a target location to a boundary of the bounding box.

7. The method of claim 1, the determining a back-end-of-line variation parameter comprising:

deriving the back-end-of-line variation parameter based upon a vertical direction property corresponding to a vertical distance from a target location to a boundary of the bounding box.

8. The method of claim 1, the determining a back-end-of-line variation parameter comprising:

deriving the back-end-of-line variation parameter based upon an omni-direction property corresponding to omni-directional distances from a target location to one or more boundaries of the bounding box.

9. The method of claim 1, the back-end-of-line variation parameter comprising a variable value corresponding to distance to one or more boundaries of the bounding box.

10. The method of claim 1, the applying the back-end-of-line variation parameter comprising:

determining a parasitic resistance based upon the back-end-of-line variation parameter.

11. The method of claim 1, the applying the back-end-of-line variation parameter comprising:

determining a parasitic capacitance based upon the back-end-of-line variation parameter.

12. The method of claim 1, wherein the size of the bounding box is a function of a device characteristic of the device.

13. The method of claim 12, the device characteristic comprising at least one of a device type, a device length, or a device width.

14. The method of claim 1, comprising:

determining a middle-end-of-line variation parameter for the bounding box; and

applying the middle-end-of-line variation parameter as a middle-end-of-line constraint for the simulation of the design layout.

15. A computer readable medium comprising instructions which when executed by a processing unit of a computing device perform a method for middle-end-of-line variation modeling, comprising:

defining a bounding box for a device within a design layout of a semiconductor arrangement, wherein a size of the bounding box is a function of patterns surrounding the device;

determining a middle-end-of-line variation parameter for the bounding box; and

applying the middle-end-of-line variation parameter as a middle -end-of-line constraint for simulation of the design layout, wherein the design layout is implemented in fabrication of the device.

16. The method of claim 15, comprising:

determining a back-end-of-line variation parameter for the bounding box; and

applying the back-end-of-line variation parameter as a back-end-of-line constraint for the simulation of the design layout.

17. The method of claim 15, the determining a middle-end-of-line variation parameter comprising:

deriving the middle-end-of-line variation parameter based upon at least one of a middle-end-of-line layer property, a middle-end-of-line density, a middle-end-of-line color property, or a middle-end-of-line corner.

18. The method of claim 15, the determining a middle-end-of-line variation parameter comprising:

deriving the middle-end-of-line variation parameter based upon at least one of;

a horizontal direction property corresponding to a horizontal distance from a target location to a first boundary of the bounding box;

a vertical direction property corresponding to a vertical distance from the target location to a second boundary of the bounding box;

or

an omni-direction property corresponding to omni-directional distances from the target location to one or more boundaries of the bounding box.

19. The method of claim 15, wherein the size of the bounding box is a function of at least one of a device type, a device length, or a device width of the device.

20. A system for back-end-of-line and middle-end-of-line variation modeling, comprising:

a variation parameter component configured to;

define a bounding box for a device within a design layout of a semiconductor arrangement, wherein a size of the bounding box is a function of patterns surrounding the device;

determine a back-end-of-line variation parameter for the bounding box; and

determine a middle-end-of-line variation parameter for the bounding box; and

a simulation component configured to;

apply the back-end-of-line variation parameter as a back-end-of-line constraint and the middle-end-of-line variation parameter as a middle-end-of-line constraint for simulation of the design layout, wherein the design layout is implemented in fabrication of the device.