Bitstream confirmation for configuration of a programmable logic device

• US 9,367,693 B2
• Filed: 06/26/2015
• Issued: 06/14/2016
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Cryptography Research, Inc. (Rambus Inc.)
• Original Assignee: Cryptography Research, Inc. (Rambus Inc.)
• Inventors: Kocher, Paul C., Rohatgi, Pankaj, Jaffe, Joshua M.
• Primary Examiner(s): Song, Hosuk
• Application Number:
  US14/752,677
• Publication Number:
  US 20160026826A1
• Time in Patent Office: 354 Days
• Field of Search: 380/277, 380/286, 380/29, 713/168, 713/174, 713/181, 713/189, 713/193, 713/194, 726/26, 726/30
• US Class Current: 1/1
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/556 involving covert channels, i.e. data leakage between processes inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 2212/402 Encrypted data
• CPC Class Codes: G06F 2221/034 Test or assess a computer or a system
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06F 2221/2125 Just-in-time application of countermeasures, e.g., on-the-fly decryption, just-in-time obfuscation or de-obfuscation
• CPC Class Codes: G06F 2221/2145 Inheriting rights or properties, e.g., propagation of permissions or restrictions within a hierarchy
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: H04L 2209/24 Key scheduling, i.e. generating round keys or sub-keys for block encryption
• CPC Class Codes: H04L 2209/56 Financial cryptography, e.g. electronic payment or e-cash
• CPC Class Codes: H04L 2463/061 applying further key derivation, e.g. deriving traffic keys from a pair-wise master key cryptographic mechanisms or cryptographic arrangements for generation of secret information including derivation or calculation of cryptographic keys or passwords H04L9/0861
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload
• CPC Class Codes: H04L 63/0869 for achieving mutual authentication cryptographic mechanisms or cryptographic arrangements for mutual authentication H04L9/3273
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/085 : Secret sharing or secret splitting, e.g. threshold schemes
• CPC Class Codes: H04L 9/0861 : Generation of secret information including derivation or calculation of cryptographic keys or passwords
• CPC Class Codes: H04L 9/088 : Usage controlling of secret information, e.g. techniques for restricting cryptographic keys to pre-authorized uses, different access levels, validity of crypto-period, different key- or password length, or different strong and weak cryptographic algorithms network architectures or network communication protocols for using time-dependent keys in a packet data network H04L63/068
• CPC Class Codes: H04L 9/0894 : Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage
• CPC Class Codes: H04L 9/16 : the keys or algorithms being changed during operation
• CPC Class Codes: H04L 9/3236 : using cryptographic hash functions
• CPC Class Codes: H04L 9/3247 : involving digital signatures
• CPC Class Codes: H04L 9/3271 : using challenge-response
• CPC Class Codes: H04L 9/50 : using hash chains, e.g. blockchains or hash trees

Abstract

A bitstream for configuration of a programmable logic device is received, the bitstream comprising a data segment and authentication data associated with the data segment. The programmable logic device computes a hash of the data segment. The programmable logic device compares the computed hash of the data segment with the authentication data. Configuration of the programmable logic device halts responsive to a determination that the computed hash of the data segment does not match the authentication data. Configuration of the programmable logic device using the data segment continues responsive to a determination that the computed hash of the data segment matches the authentication data.

Claims

1. A method comprising:

receiving a bitstream for configuration of a programmable logic device, the bitstream comprising a data segment and authentication data associated with the data segment;

computing, by the programmable logic device, a hash of the data segment;

comparing, by the programmable logic device, the computed hash of the data segment with the authentication data;

halting configuration of the programmable logic device responsive to a determination that the computed hash of the data segment does not match the authentication data; and

continuing configuration of the programmable logic device using the data segment responsive to a determination that the computed hash of the data segment matches the authentication data.

2. The method of claim 1, wherein the authentication data comprises an expected hash of the data segment.

3. The method of claim 1, wherein the programmable logic device comprises a field programmable gate array (FPGA).

4. The method of claim 1, wherein the bitstream further comprises an additional data segment, the method further comprising:

configuring the programmable logic device using the data segment;

determining whether the additional data segment has been altered using the authentication data;

halting configuration of the programmable logic device responsive to a determination that the additional data segment has been altered; and

continuing configuration of the programmable logic device using the additional data segment responsive to a determination that the additional data segment has not been altered.

5. The method of claim 4, wherein the bitstream comprises a plurality of data segments that include the data segment and the additional data segment, the method further comprising:

preventing operation of the programmable logic device until all of the plurality of data segments have been successfully used to configure the programmable logic device.

6. The method of claim 1, wherein computing the hash of the data segment is performed using an SHA-256 message authentication code (MAC) algorithm.

7. The method of claim 1, further comprising:

decrypting the data segment based on use of a shared symmetric key stored at the programmable logic device.

8. The method of claim 7, wherein the decrypting is performed using an advanced encryption standard (AES) block cipher.

9. The method of claim 7, wherein comparing the computed hash of the data segment with the authentication data is performed prior to decrypting the data segment.

10. A programmable logic device, comprising:

a plurality of programmable regions;

an interface to receive a bitstream for configuration of the plurality of programmable regions of the programmable logic device, the bitstream comprising a data segment and authentication data associated with the data segment; and

a processing component, coupled to the interface, to;

compute a hash of the data segment;

compare the computed hash of the data segment with the authentication data;

halt configuration of the programmable logic device responsive to a determination that the computed hash of the data segment does not match the authentication data; and

continue configuration of the programmable logic device using the data segment responsive to a determination that the computed hash of the data segment matches the authentication data.

11. The programmable logic device of claim 10, wherein the authentication data comprises an expected hash of the data segment.

12. The programmable logic device of claim 10, wherein the programmable logic device comprises a field programmable gate array (FPGA).

13. The programmable logic device of claim 10, wherein the bitstream further comprises an additional data segment, and wherein the processing component is further to:

configure the programmable logic device using the data segment;

determine whether the additional data segment has been altered using the authentication data;

halt configuration of the programmable logic device responsive to a determination that the additional data segment has been altered; and

continue configuration of the programmable logic device using the additional data segment responsive to a determination that the additional data segment has not been altered.

14. The programmable logic device of claim 13, wherein the bitstream comprises a plurality of data segments that include the data segment and the additional data segment, and wherein the processing component is further to:

prevent operation of the programmable logic device until all of the plurality of data segments have been successfully used to configure the programmable logic device.

15. The programmable logic device of claim 10, wherein an SHA-256 message authentication code (MAC) algorithm is used to compute the hash of the data segment.

16. The programmable logic device of claim 10, further comprising:

A memory to store a shared symmetric key, wherein the processing component is further to decrypt the data segment based on use of the shared symmetric key.

17. The programmable logic device of claim 16, wherein to decrypt the data segment the processing component uses an advanced encryption standard (AES) block cipher.

18. The programmable logic device of claim 16, wherein the processing component is to compare the computed hash of the data segment with the authentication data prior to decrypting the data segment.

19. A non-transitory computer readable medium comprising instructions that, when executed by a programmable logic device, cause the programmable logic device to perform operations comprising:

receiving a bitstream for configuration of the programmable logic device, the bitstream comprising a data segment and authentication data associated with the data segment;

computing, by the programmable logic device, a hash of the data segment;

comparing, by the programmable logic device, the computed hash of the data segment with the authentication data;

halting configuration of the programmable logic device responsive to a determination that the computed hash of the data segment does not match the authentication data; and

continuing configuration of the programmable logic device using the data segment responsive to a determination that the computed hash of the data segment matches the authentication data.

20. The non-transitory computer readable medium of claim 19, the operations further comprising:

decrypting the data segment based on use of a shared symmetric key stored at the programmable logic device.