Programmable peak-current control in non-volatile memory devices
First Claim
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1. A method, comprising:
- in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device, wherein the memory device includes a memory having a plurality of memory blocks;
configuring the memory dependent upon the peak power consumption specified in the command;
receiving a data storage command for a plurality of memory cells in a given memory block in the configured memory;
dividing the data storage command into a plurality of operations, wherein each of the plurality of operations is performed on a respective subset of a plurality of subsets of the plurality of memory cells; and
staggering a start of each of the plurality of operations to begin at respective different times.
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Abstract
A method includes, in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device. A memory of the memory device is configured in accordance with the peak power consumption specified in the command. A data storage operation in the configured memory is performed, while complying with the specified peak power consumption.
15 Citations
20 Claims
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1. A method, comprising:
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in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device, wherein the memory device includes a memory having a plurality of memory blocks; configuring the memory dependent upon the peak power consumption specified in the command; receiving a data storage command for a plurality of memory cells in a given memory block in the configured memory; dividing the data storage command into a plurality of operations, wherein each of the plurality of operations is performed on a respective subset of a plurality of subsets of the plurality of memory cells; and staggering a start of each of the plurality of operations to begin at respective different times. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus, comprising:
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a memory including a plurality of memory blocks; and circuitry, which is configured to; receive a command that specifies a peak power consumption that is not to be exceeded by the memory; configure the memory dependent upon the peak power consumption specified in the command; receive a data storage command for a plurality of memory cells in a given memory block of the plurality of memory blocks in the configured memory; divide the data storage command into a plurality of operations, wherein each of the plurality of operations is performed on a respective subset of a plurality of subsets of the plurality of memory cells; and stagger a start of each of the plurality of operations to begin at respective different times. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. An apparatus comprising:
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a first interface, which is configured to communicate with a memory, wherein the memory includes a plurality of memory blocks; a second interface, which is configured to communicate with a host processor; and a memory processor, which is configured to; receive, via the second interface, a command that specifies a peak power consumption that is not to be exceeded by the memory; configure the memory dependent upon the peak power consumption specified in the command; receive a data storage command for a plurality of memory cells in a given memory block of the plurality of memory blocks in the configured memory; divide the data storage command into a plurality of operations, wherein each of the plurality of operations is performed on a respective subset of a plurality of subsets of the plurality of memory cells; and stagger a start of each of the plurality of operations to begin at respective different times. - View Dependent Claims (19, 20)
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Specification