Self-adjusting regulation current for memory array source line

• US 9,368,224 B2
• Filed: 02/07/2014
• Issued: 06/14/2016
• Est. Priority Date: 02/07/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Wang, Sung-En, Huynh, Jonathan, Choi, Steve, Park, Jongmin
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): RADKE, JAY W
• Application Number:
  US14/175,196
• Publication Number:
  US 20150228351A1
• Time in Patent Office: 858 Days
• Field of Search: 365/185.21, 365/185.25
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

To maintain stability of memory array operations, a supplemental current can supply a common source line of a memory array so that the combined current from the memory array and supplemental current is at least a minimum regulation current level. When enabled for sensing operations, a driver circuit maintains the common source line'"'"'s voltage level. A current subtractor circuit determines the difference between a reference current and a current proportional to the current flowing from the array, where the reference current is proportional to the minimum regulation current. The difference current is then mirrored by a self-adjusting current loop and supplied to the common source line to maintain its current level.

Claims

1. A non-volatile memory circuit, comprising:

an array of non-volatile memory cells arranged along a plurality of bit lines connected to a common source line;

a pull down device connected between the common source line and ground;

an op-amp having a first input connected to the common source line, a second input connected to receive a reference level, and an output connected to a control terminal of the pull down device;

a current subtraction circuit connected to receive a reference current and the output of the op-amp and to generate therefrom a difference current having a value dependent on an amount of current from the array to the common source line relative to the reference current; and

a mirroring circuit connected to the current subtraction circuit and to the common source line to provide a supplemental current to supplement the current from the array, wherein the supplemental current is proportional to the difference current.

2. The non-volatile memory circuit of claim 1, wherein the supplemental current supplements the current from the array to the common source line to maintain a current to the pull down device above a minimum level.

3. The non-volatile memory circuit of claim 2, wherein the reference current is proportional to the minimum level.

4. The non-volatile memory circuit of claim 1, wherein the current subtraction circuit comprises a first transistor and a second transistor connected between a node supplied by the reference current and ground, and wherein a gate of the first transistor is connected to the output of the op-amp and a gate of the second transistor is connected to the node.

5. The non-volatile memory circuit of claim 1, wherein the second transistor is sized smaller than the first transistor, and wherein the reference current is smaller than a minimum level by the same ratio as that of the second transistor relative to the first transistor.

6. The non-volatile memory circuit of claim 4, wherein, for values of the current from the array to the common source line below a minimum level, a current through the second transistor is the reference current less an amount proportional to the current from the array.

7. The non-volatile memory circuit of claim 4, wherein the second transistor is sized smaller than the first transistor.

8. The non-volatile memory circuit of claim 4, wherein the mirroring circuit mirrors the current in the second transistor to generate the supplemental current.

9. The non-volatile memory circuit of claim 1, wherein the supplemental current supplements the current from the array to the common source line to maintain a current to the pull down device at a level proportional to the reference current.

10. The non-volatile memory circuit of claim 1, wherein the pull down device comprises a transistor connected between the common source line and ground and having a gate connected to receive the output of the op-amp.

11. The non-volatile memory circuit of claim 1, wherein the array of non-volatile memory cells is formed according to a NAND type architecture.

12. The non-volatile memory circuit of claim 1, wherein the array of non-volatile memory cells is formed according to a two-dimensional structure.

13. The non-volatile memory circuit of claim 1, wherein the array of non-volatile memory cells is formed according to a three-dimensional structure.

14. A current adjustment circuit, comprising:

a pull down device coupled to a circuit node;

an op-amp configured to control the pull down device;

a current subtractor circuit configured to receive a reference current and to generate a difference current based on a difference between the reference current and a current entering the circuit node; and

a current mirror circuit coupled to the pull down device and the circuit node and configured to provide a supplemental current to supplement the current entering the circuit node, wherein the supplemental current is proportional to the difference current.

15. The current adjustment circuit of claim 14, wherein the current subtractor circuit comprises a first transistor and a second transistor connected between a node supplied by the reference circuit and ground.

16. The current adjustment circuit of claim 15, wherein the second transistor is sized smaller than the first transistor.

17. The current adjustment circuit of claim 15, wherein the current mirror circuit is configured to mirror the current through the second transistor to provide the supplemental current.

18. The current adjustment circuit of claim 15, wherein the second transistor is sized smaller than the first transistor, and wherein the reference current is smaller than a minimum level by the same ratio as that of the second transistor relative to the first transistor.

19. The current adjustment circuit of claim 14, wherein the circuit node is a common source line associated with a memory array, and wherein the supplemental current supplements the current entering the circuit node to maintain a current to the pull down device above a minimum level.

20. The current adjustment circuit of claim 14, wherein the circuit node is a common source line associated with a memory array, and wherein the supplemental current supplements the current entering the circuit node to maintain a current to the pull down device at a level proportional to the reference current.