Integrated circuits and methods for operating integrated circuits with non-volatile memory

• US 9,368,506 B2
• Filed: 06/17/2015
• Issued: 06/14/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Mikalo, Ricardo Pablo, Flachowsky, Stefan
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/741,528
• Publication Number:
  US 20150333080A1
• Time in Patent Office: 363 Days
• Field of Search: 365/185.05, 365/185.14, 365/185.26
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

Claims

1. An integrated circuit comprising:

a semiconductor substrate comprising a semiconductive layer and a bottom insulative layer disposed below the semiconductive layer, the semiconductive layer having formed therein;

a first well doped with a first conductivity determining impurity;

source and drain regions disposed adjacent to the first well and doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, wherein the source and drain regions extend entirely through the semiconductive layer so as to be in contact with the bottom insulative layer;

a second well spaced apart from the first well by an insulating trench and doped with the first conductivity-determining impurity; and

a plurality of highly-doped regions formed within the second well that extend entirely through the semiconductive layer so as to be in contact with the bottom insulative layer;

a floating gate structure formed over the semiconductor substrate and comprising;

a first gate element disposed over the first well and being separated from the first well with a dielectric layer;

a second gate element disposed over the second well and being separated from the second well with the dielectric layer, wherein the second gate element comprises at least two prongs that extend substantially parallel to one another from a common base portion of the second gate element, each of the at least two prongs being disposed over a separate portion of the second well and between ones of the plurality of highly-doped regions; and

a conductive connector that electrically connects the first and second gate elements;

a first terminal formed of an electrical contact to the first well; and

a second terminal formed of electrical contacts to the second well.

2. The integrated circuit of claim 1, wherein the semiconductor substrate is a silicon-on-insulator substrate.

3. The integrated circuit of claim 1, wherein the semiconductor substrate further comprises a carrier silicon layer disposed below the insulative layer.

4. The integrated circuit of claim 3, wherein the insulative layer dielectrically separates the first and second wells from the carrier silicon layer.

5. The integrated circuit of claim 3, wherein the insulating trench is disposed over and in contact with the bottom insulative layer and separated a distance from the carrier silicon layer by the bottom insulative layer.

6. The integrated circuit of claim 1, wherein the first conductivity determining impurity is a p-type impurity.

7. The integrated circuit of claim 6, wherein the second conductivity determining impurity is an n-type impurity.

8. The integrated circuit of claim 1, wherein the first and second gate elements comprise polysilicon.

9. The integrated circuit of claim 1 comprising at least three highly-doped regions formed within the second well.

10. The integrated circuit of claim 1, wherein the bottom insulative layer comprises a silicon oxide.

11. The integrated circuit of claim 1, further comprising electrical contacts to each of the source and drain regions.

12. The integrated circuit of claim 11, further comprising an overlying conductive layer, apart from the conductive connector, in electrical connection with the electrical contacts to each of the source and drain regions.

13. The integrated circuit of claim 11, wherein the second terminal comprises electrical contacts to each of the plurality of highly-doped regions of the second well.

14. The integrated circuit of claim 13, wherein the electrical contacts to each of the plurality of highly-doped regions are separate and apart from the conductive connector.

15. The integrated circuit of claim 1, wherein the integrated circuit excludes a triple-well structure.

16. The integrated circuit of claim 1, wherein the first gate element forms a portion of a transistor.

17. The integrated circuit of claim 16, wherein the second gate element forms a portion of a control capacitor.

18. The integrated circuit of claim 16, wherein the transistor and the control capacitor form a portion of a memory cell.

19. The integrated circuit of claim 18, wherein the memory cell excludes a dual-level polysilicon architecture.