Thin film transistor array panel and method of manufacturing the same

• US 9,368,515 B2
• Filed: 11/04/2013
• Issued: 06/14/2016
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Lee, Ji Seon, Kim, Dong Jo, Lee, Jong Chan, Khang, Yoon Ho, Park, Sang Ho, Lee, Yong Su, Lee, Jung Kyu
• Primary Examiner(s): Mondt, Johannes P
• Application Number:
  US14/070,886
• Publication Number:
  US 20140175429A1
• Time in Patent Office: 953 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.

Claims

1. A thin film transistor array panel, comprising:

a channel layer comprising an oxide semiconductor and formed in a semiconductor layer;

a source electrode formed in the semiconductor layer and connected to the channel layer at a first side of the channel layer;

a drain electrode formed in the semiconductor layer and connected to the channel layer at a second side of the channel layer, opposing the first side;

a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode;

an insulating layer disposed on the channel layer;

a gate line comprising a gate electrode disposed on the insulating layer;

a passivation layer disposed on the source electrode, the drain electrode, the pixel electrode, and the gate line; and

a data line disposed on the passivation layer,

wherein a width of the channel layer is substantially equal to a width of the pixel electrode in a direction parallel to the gate line,

wherein the source electrode, the channel layer, the drain electrode and the pixel electrode are disposed in a same plane extending in a straight line below the gate electrode,

wherein the insulating layer covers the channel layer and does not extend beyond end portions of the channel layer,

wherein the insulating layer is not overlapped with the source electrode, the drain electrode, and the pixel electrode, and wherein the source electrode and the drain electrode are not overlapped with the channel layer and the gate electrode.

2. The thin film transistor array panel of claim 1, wherein:

a length of the channel layer is substantially equal to a width of the gate electrode in a direction parallel to the data line.

3. The thin film transistor array panel of claim 2, wherein:

the source electrode, the drain electrode, and the pixel electrode comprise a reduced substance reduced from a material of the oxide semiconductor.

4. The thin film transistor array panel of claim 3, wherein:

an edge boundary of the gate electrode and an edge boundary of the insulating layer are substantially aligned.

5. The thin film transistor array panel of claim 4, wherein:

the passivation layer comprises a contact hole exposing the source electrode, and

the data line is connected to the source electrode through the contact hole.

6. The thin film transistor array panel of claim 5, wherein:

the contact hole is formed at a position where the data line overlaps the passivation layer and the source electrode.

7. The thin film transistor array panel of claim 1, wherein:

the source electrode, the drain electrode, and the pixel electrode comprise a reduced substance reduced from a material of the oxide semiconductor.

8. The thin film transistor array panel of claim 7, wherein:

an edge boundary of the gate electrode and an edge boundary of the insulating layer are substantially aligned.

9. The thin film transistor array panel of claim 8, wherein:

the passivation layer comprises a contact hole exposing the source electrode, and

the data line is connected to the source electrode through the contact hole.

10. The thin film transistor array panel of claim 9, wherein:

the contact hole is formed at a position where the data line overlaps the passivation layer and the source electrode.

11. The thin film transistor array panel of claim 1, wherein:

an edge boundary of the gate electrode and an edge boundary of the insulating layer are substantially aligned.

12. The thin film transistor array panel of claim 11, wherein:

the passivation layer comprises a contact hole exposing the source electrode, and

the data line is connected to the source electrode through the contact hole.

13. The thin film transistor array panel of claim 12, wherein:

the contact hole is formed at a position where the data line overlaps the passivation layer and the source electrode.

14. The thin film transistor array panel of claim 1, wherein:

the passivation layer comprises a contact hole exposing the source electrode, and

the data line is connected to the source electrode through the contact hole.

15. The thin film transistor array panel of claim 14, wherein:

the contact hole is formed at a position where the data line overlaps the passivation layer and the source electrode.

16. A method of manufacturing a thin film transistor array panel, comprising:

forming an oxide semiconductor layer on an insulation substrate;

forming an insulating layer and a gate line comprising a gate electrode on the oxide semiconductor layer;

forming a channel layer, a source electrode, a drain electrode, and a pixel electrode in the oxide semiconductor layer by performing a reduction process on an exposed portion of the oxide semiconductor layer,

wherein the channel layer is covered by the gate electrode, the source electrode is formed at a first side of the channel layer, the drain electrode is formed at a second side of the channel layer, opposing the first side, and wherein the pixel electrode and the drain electrode are formed in a same portion of the oxide semiconductor layer, and the exposed portion of the oxide semiconductor layer is not covered by the insulating layer and the gate line;

forming a passivation layer on the source electrode, the drain electrode, the pixel electrode, and the gate line; and

forming a data line on the passivation layer,

wherein a width of the channel layer is formed to be substantially equal to a width of the pixel electrode in a direction parallel to the gate line,

wherein the source electrode, the channel layer, the drain electrode and the pixel electrode are disposed in a same plane extending in a straight line below the gate electrode,

wherein the insulating layer covers the channel layer and does not extend beyond end portions of the channel layer,

wherein the insulating layer is not overlapped with the source electrode, the drain electrode, and the pixel electrode, and the source electrode and the drain electrode are not overlapped with the channel layer and the gate electrode.

17. The method of claim 16, wherein:

a length of the channel layer is formed to be substantially equal to a width of the gate electrode in a direction parallel to the data line.

18. The method of claim 17, wherein:

forming the source electrode, the drain electrode, and the pixel electrode comprises performing a plasma process on a material of the oxide semiconductor layer to reduce the material.

19. The method of claim 18, wherein:

forming the insulating layer and the gate line comprising the gate electrode comprises

forming the insulating layer comprising an insulating material on the oxide semiconductor layer,

forming the gate line comprising the gate electrode on the insulating layer, and

patterning the insulating layer using the gate electrode as an etching mask.

20. The method of claim 19, wherein:

forming the passivation layer further comprises forming a contact hole in the passivation layer, wherein the contact hole exposes the source electrode, and

forming the data line comprises connecting the source electrode and the data line through the contact hole.

21. The method of claim 20, wherein:

forming the contact hole comprises forming the contact hole at a position where the data line overlaps the passivation layer and the source electrode.

22. The method of claim 16, wherein:

forming the source electrode, the drain electrode, and the pixel electrode comprises performing a plasma process on a material of the oxide semiconductor layer to reduce the material.

23. The method of claim 22, wherein:

forming the insulating layer and the gate line comprising the gate electrode comprises

forming the insulating layer comprising an insulating material on the oxide semiconductor layer,

forming the gate line comprising the gate electrode on the insulating layer, and

patterning the insulating layer using the gate electrode as an etching mask.

24. The method of claim 23, wherein:

forming the passivation layer further comprises forming a contact hole in the passivation layer, wherein the contact hole exposes the source electrode, and

forming the data line comprises connecting the source electrode and the data line through the contact hole.

25. The method of claim 24, wherein:

forming the contact hole comprises forming the contact hole at a position where the data line overlaps the passivation layer and the source electrode.

26. The method of claim 16, wherein:

forming the insulating layer and the gate line comprising the gate electrode comprises

forming the insulating layer comprising an insulating material on the oxide semiconductor layer,

forming the gate line comprising the gate electrode on the insulating layer, and

patterning the insulating layer using the gate electrode as an etching mask.

27. The method of claim 26, wherein:

forming the passivation layer further comprises forming a contact hole in the passivation layer, wherein the contact hole exposes the source electrode, and

forming the data line comprises connecting the source electrode and the data line through the contact hole.

28. The method of claim 27, wherein:

forming the contact hole comprises forming the contact hole at a position where the data line overlaps the passivation layer and the source electrode.

29. The method of claim 16, wherein:

forming the passivation layer further comprises forming a contact hole in the passivation layer, wherein the contact hole exposes the source electrode, and

forming the data line comprises connecting the source electrode and the data line through the contact hole.

30. The method of claim 29, wherein:

forming the contact hole comprises forming the contact hole at a position where the data line overlaps the passivation layer and the source electrode.