Field effect transistor with narrow bandgap source and drain regions and method of fabrication
First Claim
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1. A transistor comprising:
- a gate dielectric layer formed over a substrate;
a gate electrode formed on the gate dielectric layer; and
a pair of source/drain regions on opposite sides of the gate electrode, the pair of source/drain regions comprising a doped semiconductor film that extends above a top surface of a silicon layer on which the gate dielectric layer is deposited, wherein the semiconductor film comprises a material selected from the group consisting of InSb, InAs, InP and InGaAs; and
wherein the semiconductor film is doped to an n-type conductivity with a silicon (Si), a tellurium (Te), or a sulfur (S) dopant.
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Abstract
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
601 Citations
19 Claims
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1. A transistor comprising:
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a gate dielectric layer formed over a substrate; a gate electrode formed on the gate dielectric layer; and a pair of source/drain regions on opposite sides of the gate electrode, the pair of source/drain regions comprising a doped semiconductor film that extends above a top surface of a silicon layer on which the gate dielectric layer is deposited, wherein the semiconductor film comprises a material selected from the group consisting of InSb, InAs, InP and InGaAs; and
wherein the semiconductor film is doped to an n-type conductivity with a silicon (Si), a tellurium (Te), or a sulfur (S) dopant. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A transistor comprising:
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a substrate comprising a body having a top surface opposite a bottom surface and a pair of sidewalls; a gate dielectric layer on the body along the top surface and the pair of sidewalls of the body; a gate electrode on the gate dielectric layer along the top surface and the pair of sidewalls of the body; and a pair of non-planar source/drain regions on the body on opposite sides of the gate electrode, the pair of non-planar source/drain regions comprising an in situ doped semiconductor film comprising a material selected from the group consisting of InSb, InAs, InP and InGaAs that extends above the top surface on which the gate dielectric layer is deposited, wherein the semiconductor film is doped to an n-type conductivity with a silicon (Si) dopant. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification