Accumulation-mode field effect transistor with improved current capability

• US 9,368,587 B2
• Filed: 05/31/2014
• Issued: 06/14/2016
• Est. Priority Date: 01/30/2001
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher Boguslaw, Shenoy, Praveen Muraleedharan
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US14/292,894
• Publication Number:
  US 20140264573A1
• Time in Patent Office: 745 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An accumulation-mode field effect transistor including a plurality of gates. The accumulation-mode field effect transistor including a semiconductor region including a channel region adjacent to but insulated from each of the plurality of gates.

Claims

1. An accumulation-mode field effect transistor, comprising:

a plurality of gates;

a semiconductor region including a plurality of channel regions adjacent to but insulated from each of the plurality of gates, and a drift region,

the plurality of channel regions and the drift region being of a first conductivity type;

a drain terminal and a source terminal configured so that when the accumulation-mode field effect transistor is in the on state a current flows from the drain terminal to the source terminal through the drift region and the channel regions; and

a plurality of insulation-filled trenches extending into the semiconductor region adjacent to the drift region, at least one sidewall of each insulation-filled trench being lined with silicon material of a second conductivity type opposite the first conductivity type.

2. The accumulation-mode field effect transistor of claim 1, wherein the sidewalls and bottom of each insulation-filled trench is lined with silicon material of the second conductivity type.

3. The accumulation-mode field effect transistor of claim 1, wherein opposite sidewalls of each insulation-filled trench are lined with opposite conductivity type silicon material.

4. The accumulation-mode field effect transistor of claim 1, further comprising:

a plurality of gate trenches extending in the semiconductor region, each of the plurality of gate trenches having one of the plurality of gates disposed therein, the plurality of gate trenches and insulation-filled trenches being alternately arranged so that each of the plurality of channel region separates one insulation-filled trench from an adjacent gate trench, the plurality of insulation-filled trenches extending deeper in the semiconductor region than the plurality of gate trenches.

5. The accumulation-mode field effect transistor of claim 4, wherein each of the plurality of channel regions includes a plurality of regions of the second conductivity type, each of the plurality of regions of the second conductivity type laterally extending to abut the insulation-filled trench and the gate trench between which each of the plurality of regions of the second conductivity type are located.

6. The accumulation-mode field effect transistor of claim 4, wherein each of the plurality of channel regions includes a region of the first conductivity type, each of the regions laterally extending to abut at least one of the insulation-filled trench and at least one of the gate trenches, each of the regions having a doping concentration higher than that of the plurality of channel regions.

7. The accumulation-mode field effect transistor of claim 4, wherein each of the plurality of channel regions includes a first region of the first conductivity type and a second region of the first conductivity type, the first regions and the second regions each having a doping concentration higher than that of the plurality of channel regions.

8. An accumulation-mode field effect transistor, comprising:

a gate;

a semiconductor region including;

a channel region adjacent to but insulated from the gate, and

a drift region, the channel region and the drift region having of a first conductivity type;

a drain terminal and a source terminal configured so that when the accumulation-mode field effect transistor is in the on state a current flows from the drain terminal to the source terminal through the drift region and the channel region; and

a trench extending into the semiconductor region adjacent to the drift region, a sidewall of the trench being lined with a silicon material of a second conductivity type opposite the first conductivity type.

9. The accumulation-mode field effect transistor of claim 8, wherein a bottom of the trench is lined with the silicon material of the second conductivity type.

10. The accumulation-mode field effect transistor of claim 8, wherein the trench is an insulation-filled trench.

11. The accumulation-mode field effect transistor of claim 8, wherein the sidewall is a first sidewall of trench,

the accumulation-mode field effect transistor further comprising:

a second sidewall of the trench lined with a silicon material of a the first conductivity type.

12. The accumulation-mode field effect transistor of claim 8, further comprising:

a gate trench extending in the semiconductor region, the gate trench having the gate disposed therein, the trench being an insulation-filled trench adjacent to the gate trench, the insulation-filled trench extending deeper in the semiconductor region than the gate trench.

13. The accumulation-mode field effect transistor of claim 12, wherein the channel region includes a region of the second conductivity type, the region of the second conductivity type laterally extending to and abutting the insulation-filled trench and the gate trench.

14. An accumulation-mode field effect transistor, comprising:

a gate trench including a gate disposed therein;

a semiconductor region including;

a channel region adjacent to but insulated from the gate, and

a drift region, the channel region and the drift region of a first conductivity type;

a drain terminal and a source terminal configured so that when the accumulation-mode field effect transistor is in the on state a current flows from the drain terminal to the source terminal through the drift region and the channel region; and

a trench extending into the semiconductor region adjacent to the drift region, the trench having a depth within the semiconductor region greater than a depth of the gate trench, the trench having a sidewall lined with a dielectric.

15. The accumulation-mode field effect transistor of claim 14, wherein the trench includes at least one diode.

16. The accumulation-mode field effect transistor of claim 14, wherein a dielectric layer is not disposed along a bottom of the trench such that a bottom region of the trench is in electric contact with the drift region.