Method for fabricating a transistor with reduced junction leakage current

• US 9,368,624 B2
• Filed: 07/24/2015
• Issued: 06/14/2016
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Thompson, Scott E., Shifren, Lucian, Ranade, Pushkar, Liu, Yujie, Kim, Sung Hwan, Wang, Lingquan, Zhao, Dalong, Bakhishev, Teymur, Hoffmann, Thomas, Pradhan, Sameer, Duane, Michael
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US14/808,122
• Publication Number:
  US 20150333144A1
• Time in Patent Office: 326 Days
• Field of Search: 438/301, 438/303, 438/369
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

Claims

1. A method for fabricating a transistor with reduced junction leakage current, comprising:

forming a layered stack, the layered stack including at least a doped screening layer and an undoped channel layer over the doped screening layer;

forming a gate over the undoped channel layer, the gate having an effective gate length;

forming a source region on one side of the gate and a drain region on another side of the gate;

wherein

a depth of the doped screening layer is set a preselected distance below the gate such that the distance is a fraction of the effective gate length of the transistor, a thickness of the doped screening layer is preselected such that a bottom of the doped screening layer is above a bottom of the source region and a bottom of the drain region, the doped screen layer extends laterally to and contacts both the source region and the drain region, and further comprising;

forming a shallow lightly doped drain region in the undoped channel layer on either side of the gate and extending a defined distance inward from an outer edge of the gate; and

forming a deep lightly doped drain region on either side of the gate at a depth of the doped screening layer.