NAND string utilizing floating body memory cell

• US 9,368,625 B2
• Filed: 05/01/2014
• Issued: 06/14/2016
• Est. Priority Date: 05/01/2013
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Louie, Benjamin S., Han, Jin-Woo, Widjaja, Yuniarto
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US14/267,112
• Publication Number:
  US 20140328128A1
• Time in Patent Office: 775 Days
• Field of Search: 365/185.17, 365/185.05
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

Claims

1. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region have a first conductivity type selected from p-type conductivity type and n-type conductivity type;

said floating body region having a bottom surface bounded by an insulator layer;

a first region in electrical contact with said floating body region, said first region exposed at or proximal to a top surface of said floating body region and extending to contact said insulator layer;

a second region in electrical contact with said floating body region and spaced apart from said first region, said second region exposed at or proximal to said top surface of said floating body region and extending into said floating body region, wherein said floating body region underlies said second region such that said second region does not extend to contact said insulator layer;

a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region exposed at or proximal to said top surface of said floating body region and extending to contact said insulator layer; and

a gate positioned between said first and second regions;

wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region; and

wherein said semiconductor memory cell has only one said gate.

2. The semiconductor memory cell of claim 1, wherein said floating body is formed in a substrate having said first conductivity type and said insulator is a buried layer positioned between said bottom surface of said floating body region and a lower portion of said substrate.

3. The semiconductor memory cell of claim 2, wherein said top surface of said floating body region is a top surface of said substrate.

4. The semiconductor memory cell of claim 1, wherein said first, second and third regions have a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, and wherein said second conductivity type is different from said first conductivity type.

5. The semiconductor memory cell of claim 1, wherein said first and third regions electrically isolate said floating body region from neighboring floating body regions of adjacent ones of said semiconductor memory cell when a plurality of said semiconductor memory cells are joined in an array.

6. The semiconductor memory cell of claim 1, wherein said floating body region and said first, second and third regions are provided in a fin structure that extends vertically above said insulator layer.