Low fabrication cost, high performance, high reliability chip scale package

• US 9,369,175 B2
• Filed: 10/31/2007
• Issued: 06/14/2016
• Est. Priority Date: 09/17/2001
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lee, Jin-Yuan, Lei, Ming-Ta, Huang, Ching-Cheng, Lin, Chuen-Jye
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US11/930,213
• Publication Number:
  US 20080111236A1
• Time in Patent Office: 3,149 Days
• Field of Search: 257/737, 257/780, 257/778, 257/738
• US Class Current: 1/1
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/15 Structure, shape, material or disposition of the bump connectors after the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H04B 1/7113 : Determination of path profile
• CPC Class Codes: H04B 1/712 : Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop

Abstract

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Claims

1. A chip package comprising:

a ball grid array (BGA) substrate;

a semiconductor device comprising a first substrate having a first surface and a second surface opposite said first surface, a passivation layer on said first surface of said first substrate, a polymer layer on said passivation layer, and a conductive pad having a contact point within a first opening in said passivation layer, wherein a second opening in said polymer layer exposes said contact point;

a copper pillar structure having a first surface and a second oxidized surface opposite said first surface, said copper pillar structure having opposing oxidized sidewalls separated by a first width, said first surface of said copper pillar structure being coupled to said contact point through said second opening via a conductive interconnect, said first surface of said copper pillar structure directly on a surface of said conductive interconnect, in which each of said first surface and said second oxidized surface of said copper pillar structure have the same first width;

an underbump nickel layer having a second width greater than said first width, a first oxidized surface of said underbump nickel layer directly on said second oxidized surface of said copper pillar structure opposite said first surface of said copper pillar structure;

a solder ball directly on a second oxidized surface of said underbump nickel layer opposite said copper pillar structure and said BGA substrate, said second oxidized surface of said underbump nickel layer opposite said first oxidized surface of said underbump nickel layer;

an underfill between said semiconductor device and said BGA substrate, wherein said underfill contacts said semiconductor device and at least a portion of said BGA substrate and on said first width of said copper pillar structure and said solder ball; and

an encapsulant material on said second surface of said first substrate to encapsulate said semiconductor device, said encapsulant on said opposing oxidized sidewalls of said copper pillar structure.

2. The chip package of claim 1, wherein said polymer layer comprises polyimide.

3. The chip package of claim 1, wherein said polymer layer comprises bisbenzocyclobutene (BCB).

4. The chip package of claim 1, wherein said solder ball comprises a solder joint having a thickness between 10 and 100 micrometers.

5. A chip package comprising:

a first substrate;

a semiconductor device comprising a second substrate having a first surface and a second surface opposite said first surface, a separating layer on said first surface of said second substrate, a polymer layer on said separating layer, and a conductive pad coupled to said semiconductor device through a first opening in said separating layer, wherein a second opening in said polymer layer exposes said conductive pad;

a copper pillar structure having a first surface and a second oxidized surface opposite said first surface, said copper pillar structure having opposing oxidized sidewalls separated by a first width, said first surface of said copper pillar structure being coupled to said conductive pad through said second opening via a conductive interconnect, in which said first surface of said copper pillar structure is directly on said conductive interconnect, in which each of said first surface and said second oxidized surface of said copper pillar structure have the same first width;

an underbump nickel layer having a second width greater than said first width, a first oxidized surface of said underbump nickel layer directly on said second oxidized surface of said copper pillar structure opposite said first surface of said copper pillar structure;

a solder ball directly on a second oxidized surface of said underbump nickel layer opposite said copper pillar structure, said second oxidized surface of said underbump nickel layer opposite said first oxidized surface of said underbump nickel layer;

an underfill coupled to said semiconductor device, wherein said underfill covers a sidewall of said solder ball and a sidewall of said copper pillar structure; and

an encapsulant material on said second surface of said second substrate to encapsulate said semiconductor device, said encapsulant on said opposing oxidized sidewalls of said copper pillar structure.

6. The chip package of claim 5, wherein said polymer layer comprises polyimide.

7. The chip package of claim 5, wherein said polymer layer comprises bisbenzocyclobutene (BCB).

8. The chip package of claim 5, wherein said solder ball comprises a solder joint having a thickness between 10 and 100 micrometers.

9. A chip package comprising:

a ball grid array (BGA) substrate;

a semiconductor device comprising a first substrate having a first surface and a second surface opposite said first surface, a passivation layer on said first surface of said first substrate, a conductive pad within an opening in said passivation layer, and a conductive interconnect coupled to said passivation layer, wherein said conductive interconnect is coupled to said conductive pad through said opening;

a copper pillar structure having a first surface and a second oxidized surface opposite said first surface, said copper pillar structure having opposing oxidized sidewalls separated by a first width, said first surface of said copper pillar structure directly on said conductive interconnect, in which each of said first surface and said second oxidized surface of said copper pillar structure have the same first width;

an underbump nickel layer having a second width greater than said first width, a first oxidized surface of said underbump nickel layer directly on said second oxidized surface of said copper pillar structure opposite said first surface of said copper pillar structure;

a solder ball directly on a second oxidized surface of said underbump nickel layer opposite said copper pillar structure, said second oxidized surface of said underbump nickel layer opposite said first oxidized surface of said underbump nickel layer;

a first contact structure on said BGA substrate;

a second contact structure on said BGA substrate, in which said first and second contact structures are adjacent to each other, and no contact structure is between said first and second contact structures; and

an encapsulant material on said second surface of said first substrate to encapsulate said semiconductor device, said encapsulant on said opposing oxidized sidewalls of said copper pillar structure.

10. The chip package of claim 9, wherein said semiconductor device further comprises a polymer layer coupled to said passivation layer.

11. The chip package of claim 9, wherein said conductive interconnect comprises titanium.

12. The chip package of claim 9, wherein said conductive pad comprises copper.

13. The chip package of claim 9, wherein said conductive pad comprises aluminum.

14. The chip package of claim 9, wherein said conductive interconnect comprises a titanium-containing layer and an electroplated conductive layer coupled to said titanium-containing layer.

15. A chip package comprising:

a first substrate;

a semiconductor device coupled to said first substrate, said semiconductor device comprising a second substrate having a first surface and a second surface opposite said first surface;

a copper pillar structure having a first surface and a second oxidized surface opposite said first surface, said copper pillar structure having opposing oxidized sidewalls separated by a first width, in which each of said first surface and said second oxidized surface of said copper pillar structure have the same first width;

an underbump nickel layer having a second width greater than said first width, a first oxidized surface of said underbump nickel layer directly on said second oxidized surface of said copper pillar structure opposite said first surface of said copper pillar structure;

a solder ball directly on a second oxidized surface of said underbump nickel layer opposite said copper pillar structure and said first substrate, said second oxidized surface of said underbump nickel layer opposite said first oxidized surface of said underbump nickel layer;

an underfill between said semiconductor device and said first substrate; and

an encapsulant material on said second surface of said second substrate to encapsulate said semiconductor device, said encapsulant on said opposing oxidized sidewalls of said copper pillar structure.

16. The chip package of claim 15, wherein said semiconductor device further comprises a polymer layer disposed within said semiconductor device.

17. The chip package of claim 15, in which said semiconductor device further comprises a conductive interconnect comprising titanium disposed within said semiconductor device.

18. The chip package of claim 15, in which said semiconductor device further comprises a conductive pad comprising copper disposed within said semiconductor device.

19. The chip package of claim 15, in which said semiconductor device further comprises a conductive pad comprising aluminum disposed within said semiconductor device.

20. The chip package of claim 15, in which said semiconductor device further comprises a conductive interconnect comprising a titanium-containing layer and an electroplated conductive layer coupled to said titanium-containing layer disposed within said semiconductor device.

21. A chip package comprising:

a first substrate;

a semiconductor device comprising a second substrate having a first surface and a second surface opposite said first surface;

a copper pillar structure having a first surface and a second oxidized surface opposite said first surface, said copper pillar structure having opposing oxidized sidewalls separated by a first width, in which each of said first surface and said second oxidized surface of said copper pillar structure have the same first width;

an underbump nickel layer having a second width greater than said first width, a first oxidized surface of said underbump nickel layer directly on said second oxidized surface of said copper pillar structure opposite said first surface of said copper pillar structure;

a solder ball directly on a second oxidized surface of said underbump nickel layer opposite said copper pillar structure, said second oxidized surface of said underbump nickel layer opposite said first oxidized surface of said underbump nickel layer;

an underfill between said semiconductor device and said solder ball; and

an encapsulant material on said second surface of said second substrate to encapsulate said semiconductor device, said encapsulant on said opposing oxidized sidewalls of said copper pillar structure.

22. The chip package of claim 21, in which said semiconductor device further comprises a conductive interconnect comprising titanium disposed within said semiconductor device.

23. The chip package of claim 21, in which said semiconductor device further comprises a conductive pad comprising copper disposed within said semiconductor device.

24. The chip package of claim 21, in which said semiconductor device further comprises a conductive interconnect comprising a titanium-containing layer and an electroplated conductive layer coupled to said titanium-containing layer disposed within said semiconductor device.