System and method for fast compensation programming of pixels in a display

• US 9,370,075 B2
• Filed: 05/26/2012
• Issued: 06/14/2016
• Est. Priority Date: 12/09/2008
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, Gholamreza, Lai, Jackson Chi Sun, Azizi, Yaser, Ma, Maran Ran, Nathan, Arokia
• Primary Examiner(s): Tzeng, Fred
• Application Number:
  US13/481,789
• Publication Number:
  US 20130099692A1
• Time in Patent Office: 1,480 Days
• Field of Search: 345/204, 345/76, 345/78, 345/82, 345/211, 345/690
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2310/0259 with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/066 Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/023 using energy recovery or conservation
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: H05B 47/10 Controlling the light source
• CPC Class Codes: H05B 47/165 following a pre-assigned programmed sequence; Logic control [LC]

Abstract

Circuits for programming a circuit with decreased programming time are provided. Such circuits include a storage device such as a capacitor for storing display information and for ensuring a driving device such as a driving transistor drives a light emitting device according to the display information. To increase programming time, the pixel circuits may be pre-charged or a biasing current may be applied to charge and/or discharge a data line and/or the driving device. Aspects of the present disclosure allow for the biasing current to drain partially through the storage device to allow the portion of the biasing current applied to the driving device to remain small while the data line discharges. Furthermore, the present disclosure provides display architectures and operation schemes for display arranged in segments each including a plurality of pixel circuits.

Claims

1. A pixel circuit comprising:

a driving transistor for conveying a driving current through a light emitting device during an emission cycle, the driving current being conveyed according to programming information;

a capacitor coupled in series between a gate terminal of the driving transistor and a line conveying compensation signals; and

a switching transistor coupled between the gate terminal of the driving transistor and a terminal of the driving transistor other than the gate terminal,

wherein the capacitor and the driving transistor are coupled via the switching transistor such that while the switching transistor is turned on, a compensation current is conveyed through the driving transistor, the switching transistor, and across the storage capacitor while the gate terminal of the driving transistor adjusts according to the compensation current.

2. The pixel circuit according to claim 1, wherein the line conveying compensation signals is a line providing a changing voltage having a substantially constant time derivative such that the compensation current generated across the capacitor has a substantially constant value.

3. The pixel circuit according to claim 1, further comprising:

a second switching transistor connected in series between the gate terminal of the drive transistor and the capacitor such that the gate terminal of the driving transistor is selectively connected to the capacitor, and

a second capacitor coupled to the gate terminal of the driving transistor for being charged according to the programming information during a programming cycle preceding the emission cycle, such that the driving transistor conveys the driving current according to a charge on the second capacitor.

4. The pixel circuit according to claim 3, wherein the switching transistor is coupled to the gate terminal of the driving transistor through the second switching transistor, the switching transistor being directly connected to the capacitor.

5. The pixel circuit according to claim 4, wherein the pixel circuit is further configured to reset the capacitor by discharging voltage on the capacitor, via the switching transistor, while the second switching transistor is turned off to thereby isolate the gate terminal of the driving transistor from the capacitor during the reset.

6. The pixel circuit according to claim 5, wherein the second switching transistor is coupled to a capacitance associated with the light emitting device during the reset, and the discharge of the capacitor is carried out by discharging the capacitor to the capacitance associated with the light emitting device.

7. The pixel circuit according to claim 3, further comprising a third switching transistor connected in series with the switching transistor and operated according to select line that also operates the switching transistor such that the switching transistor is coupled to the gate terminal of the driving transistor through the third switching transistor, thereby isolating the gate terminal of the driving transistor from the current path through the light emitting device by both the switching transistor and the third switching transistor.

8. The pixel circuit according to claim 3, wherein the line conveying compensation signals is a data line providing a programming voltage according to the programming information during the programming cycle, and wherein the second switching transistor is operated by a second select line and the switching transistor is operated by a first select line such that the switching transistor and the second switching transistor are both turned on while the compensation current is conveyed through the driving transistor and such that the second switching transistor is turned on and the switching transistor is turned off while the programming voltage is applied to the data line to set the voltage of the gate terminal of the driving transistor based on the programming voltage.

9. The pixel circuit according to claim 8, further comprising an emission transistor operated according to an emission select line for selectively coupling the driving transistor to the light emitting device during the emission cycle, the emission transistor being configured to prevent the light emitting device from emitting light during the programming cycle or while the gate terminal of the driving transistor adjusts according to the compensation current.

10. The pixel circuit according to claim 1, wherein the capacitor is a storage capacitor for being charged according to programming information during a programming cycle preceding the emission cycle, such that the driving transistor conveys the driving current according to a charge on the storage capacitor.

11. The pixel circuit according to claim 1, wherein the calibration current is drained through the capacitor to a current source drawing a reference current, the reference current including the compensation current and a data line discharge current.

12. The pixel circuit according to claim 1, wherein the line conveying compensation signals is a data line configured to provide:

a programming voltage to charge the capacitor according to the programming information, and

a reference current to simultaneously drain the compensation current through the capacitor and discharge the data line.

13. The pixel circuit according to claim 12, wherein the data line is further configured to apply a reference voltage during the emission cycle to thereby reference the capacitor to the reference voltage.

14. The pixel circuit according to claim 1, wherein the line conveying compensation signals is configured to provide a reference current to the capacitor and a terminal of the driving transistor not connected to the switching transistor is connected to a data line configured to provide a programming voltage simultaneously with the reference current such that the programming voltage is conveyed through the drive transistor and the switching transistor to the capacitor simultaneously with the reference current being conveyed through the driving transistor and the switching transistor and across the capacitor.

15. The pixel circuit according to claim 1, further comprising an emission transistor operated according to an emission select line for selectively coupling the driving transistor to the light emitting device during the emission cycle, the emission transistor being configured to prevent the light emitting device from emitting light during a programming cycle.

16. The pixel circuit according to claim 1, wherein a first terminal of the capacitor, a first terminal of the switching transistor, and a gate terminal of the driving transistor are connected at a node, the node being charged, during a pre-charge cycle, while the switching transistor is turned on, with a voltage given by the difference of a supply line voltage and a threshold voltage of the driving transistor.

17. The pixel circuit according to claim 1, wherein the light emitting device is an organic light emitting diode, and wherein the driving transistor is a p-type thin film transistor.

18. A system for driving a display, the system comprising:

a pixel circuit including;

a driving transistor for driving a light emitting device to emit light according to programming information during an emission cycle;

a capacitor coupled in series between a gate terminal of the driving transistor and a line conveying compensation signals; and

a switching transistor coupled between the gate terminal of the driving transistor and a terminal of the driving transistor other than the gate terminal; and

a data driver for applying a programming voltage to the pixel circuit via a data line during a programming cycle, the data line being coupled to the pixel circuit, the programming voltage being provided according to the programming information; and

a current source or voltage ramp generator for generating a reference current or a voltage with a substantially constant rate of change on the data line or another line coupled to the pixel circuit, to thereby convey a compensation current through the driving transistor and the switching transistor and across the storage capacitor while the gate terminal of the driving transistor adjusts according to the compensation current.

19. The system according to claim 18, wherein a capacitance of the data line combines with the capacitor to form a current divider such that the reference current applied to the data line is divided between the compensation current conveyed through the capacitor and a discharge current for discharging the capacitance of the data line.

20. The system according to claim 18, wherein the pixel circuit further comprises:

a second switching transistor connected in series between a gate terminal of the driving transistor and the capacitor such that the gate terminal of the driving transistor is selectively connected to the capacitor to thereby capacitively couple the gate terminal of the driving transistor with the line conveying compensation signals, and

a second capacitor coupled to the gate terminal of the driving transistor for being charged according to the programming information during a programming cycle preceding the emission cycle, such that the driving transistor conveys the driving current according to a charge on the second capacitor.

21. The system according to claim 20, wherein the switching transistor is coupled to the gate terminal of the driving transistor through the second switching transistor, the switching transistor being directly connected to the capacitor.

22. The system according to claim 21, wherein the pixel circuit is further configured to reset the capacitor by discharging voltage on the capacitor, via the switching transistor, while the second switching transistor is turned off to thereby isolate the gate terminal of the driving transistor from the capacitor during the reset.

23. The system according to claim 22, wherein the second switching transistor is coupled to a capacitance associated with the light emitting device during the reset, and the discharge of the capacitor is carried out by discharging the capacitor to the capacitance associated with the light emitting device.

24. The system according to claim 20, further comprising a third switching transistor connected in series with the switching transistor and operated according to select line that also operates the switching transistor such that the switching transistor is coupled to the gate terminal of the driving transistor through the third switching transistor, thereby isolating the gate terminal of the driving transistor from the current path through the light emitting device by both the switching transistor and the third switching transistor.

25. The system according to claim 18, wherein the line conveying compensation signals is a data line providing a programming voltage according to the programming information during a programming cycle, and wherein the second switching transistor is operated by a second select line and the switching transistor is operated by a first select line such that the switching transistor and the second switching transistor are both turned on while the compensation current is conveyed through the driving transistor and such that the second switching transistor is turned on and the switching transistor is turned off while the programming voltage is applied to the data line to set the voltage of the gate terminal of the driving transistor based on the programming voltage.

26. The system according to claim 18, wherein the data driver includes a cyclic digital to analog converter and the voltage ramp generator includes a ramp value signal source that is selectively connected to the cyclic digital to analog converter to generate a ramp voltage on the data line via the cyclic digital to analog converter.

27. The system according to claim 18, wherein the data driver includes a resistive digital to analog converter and the voltage ramp generator is selectively connected to the data line via one or more switches while the compensation current is conveyed through the driving transistor.

28. The system according to claim 18, further comprising an address driver for controlling a select line coupled to the switching transistor, the switching transistor being operated according to the select line to selectively turn on the switching transistor during the programming cycle.

29. The system according to claim 18, further comprising a reference voltage generator for providing a reference voltage on the data line, during the emission cycle, thereby referencing the storage capacitor to the reference voltage.

30. The system according to claim 18, wherein the pixel circuit further includes an emission control transistor for selectively coupling the driving transistor to the light emitting device during the emission cycle, the emission control transistor being operated according to an emission select line so as to prevent leakage currents from driving the light emitting device during periods other than the emission cycle.

31. A display system comprising a plurality of pixel circuits arranged in rows and columns in a display array, each pixel circuit including:

a driving transistor for driving a light emitting device to emit light according to programming information during an emission cycle;

a storage capacitor coupled to the gate terminal of the driving transistor and arranged to be charged according to the programming information during a programming cycle;

a first switching transistor operated according to first select line and connected between the gate terminal of the driving transistor and a terminal of the driving transistor other than the gate terminal;

a second switching transistor operated according to a second select line and connected to the gate terminal of the driving transistor; and

wherein the gate terminal of each driving transistor being connected, through the second switching transistor, to a programming capacitor connected in series between the second switching transistor and a data line,

a data driver for applying a programming voltage to the plurality of pixel circuits via respective data lines during a programming cycle, the programming voltage being provided according to the programming information for each pixel circuit; and

a current source or voltage ramp generator for generating a reference current or a voltage with a substantially constant rate of change on the data line or another line coupled to at least one of the plurality of pixel circuits, to thereby convey a compensation current through the driving transistor and the switching transistor and across the storage capacitor while the gate terminal of the driving transistor adjusts according to the compensation current.

32. The display system according to claim 31, wherein the display array is segmented into a plurality of segments, each of the plurality of segments comprising a plurality of the plurality of pixel circuits, and wherein, within each of the plurality of segments, the programming capacitor is shared by more than one pixel circuit connected to a common data line.

33. The display system according to claim 32, wherein the first switching transistors within pixel circuits in each segment are operated according to a common segmented control line to simultaneously operate the first switching transistors in the pixel circuits in each of the plurality of segments, respectively.

34. The display system according to claim 33, wherein the segmented control lines for each segment are operated to simultaneously convey the compensation current through the pixel circuits in a segment, via the respective first switching transistors, to allow the respective driving transistors in the segment to adjust according to the compensation current, during a compensation cycle.

35. The display system according to claim 31, wherein each pixel circuit further comprises an emission control transistor operated according to an emission control line to selectively connect the driving transistor to the light emitting device, the emission control line being operated to prevent the light emitting device from emitting light while the compensation current is conveyed through the driving transistor.

36. The display system according to claim 31, wherein each pixel circuit is configured with the first switching transistor coupled to the gate terminal of the driving transistor through the second switching transistor, the first switching transistor being directly connected to the programming capacitor.

37. The display system according to claim 36, wherein each pixel circuit is further configured to reset the programming capacitor by discharging voltage on the programming capacitor, via the first switching transistor, while the second switching transistor is turned off to isolate the gate terminal of the driving transistor from the programming capacitor during the reset.

38. The display system according to claim 37, wherein each pixel circuit is configured with the second switching transistor coupled to a capacitance associated with the light emitting device during the reset, and the discharge of the capacitor is carried out by discharging the programming capacitor to the capacitance associated with the light emitting device.

39. The display system according to claim 31, wherein each pixel circuit further includes a third switching transistor connected in series with the first switching transistor and operated according to the first select line such that the first switching transistor is coupled to the gate terminal of the driving transistor through the third switching transistor, thereby isolating the gate terminal of the driving transistor from the current path through the light emitting device by both the switching transistor and the third switching transistor.

40. The display system according to claim 31, wherein the light emitting device is an organic light emitting diode and the driving transistor is a p-type thin film transistor.

41. A method of driving a display comprising:

a pixel circuit including;

a driving transistor for conveying a driving current through a light emitting device according to programming information;

a capacitor for being charged according to the programming information, the capacitor having a first terminal coupled to a first conductive line and a second terminal coupled to a gate terminal of the driving transistor, and

a switching transistor coupled between the gate terminal of the driving transistor and another terminal of the driving transistor, and

wherein the method comprises;

charging the first or second terminal of the capacitor with a programming voltage during a programming cycle while the switching transistor is selected;

applying a reference current to the first conductive line during the programming cycle such that a compensation current is drained across the capacitor and through the switching transistor and the driving transistor.

42. The method according to claim 41, wherein the compensation current adjusts a gate-source voltage of the driving transistor so as to calibrate the pixel circuit to account for a degradation of the pixel circuit.

43. The method according to claim 41, further comprising setting the first conductive line to a reference voltage level during an emission cycle that follows the program cycle such that the storage capacitor is referenced to the reference voltage.

44. The method according to claim 41, further comprising:

pre-charging the first conductive line with a programming voltage, during a pre-charging cycle included in the program cycle; and

providing a voltage with a substantially constant rate of change on the first conductive line, during a compensation cycle included in the program cycle, the voltage on the first conductive line being constantly changed due to application of the reference current simultaneously draining a discharge current to thereby simultaneously discharge a parasitic capacitance of the first conductive line and provide the compensation current across the capacitor.

45. A display system comprising:

a pixel circuit including;

a driving transistor for driving a light emitting device during an emission cycle, and

a capacitor for being charged with a proper voltage to cause the driving transistor to drive the light emitting device according to programming information;

a data driver for applying a programming voltage to the pixel circuit via a data line during a programming cycle, the data line being coupled to the pixel circuit, the programming voltage being provided according to the programming information; and

a current source for applying a reference current to a bias line during the programming cycle and thereby draining a compensation current through the driving transistor and across the capacitor while simultaneously discharging the data line.

46. The display system according to claim 45, wherein the pixel circuit further comprises an emission control transistor configured to selectively allow current to flow through the light emitting device and wherein the data line is coupled to a first terminal of the driving transistor, a second terminal of the driving transistor being coupled to the light emitting device via the emission control transistor, the pixel circuit further including a switching transistor providing a current path for the compensation current to flow through the drive transistor and across the capacitor.

47. The display system according to claim 45, wherein the capacitor and the capacitance of the data line are arranged to divide the reference current such that a first portion discharges the capacitance associated with the data line while a second portion calibrates the pixel circuit by providing the compensation current.

48. The display system according to claim 47, wherein the reference current is divided according to the capacitance of the data line and the capacitance of the capacitor.

49. A method of operating a display having a pixel circuit for driving a light emitting device, the method comprising:

pre-charging the pixel circuit, during a pre-charge cycle, by turning on a switching transistor such that a voltage given by a difference between a supply line voltage and a threshold voltage of a driving transistor is charged on a node of the pixel circuit coupled to both a capacitor and the gate terminal of the driving transistor;

conveying a compensation current through the driving transistor, the switching transistor, and across the capacitor, during a compensation cycle, to allow the driving transistor to adjust the voltage of the node to allow the compensation current to be conveyed; and

applying a reference voltage to a terminal of the capacitor other than a terminal of the capacitor coupled to the node, during an emission cycle during which the pixel circuit is driven to emit light according to programming information.

50. The method according to claim 49, wherein the compensation current adjusts a gate-source voltage of the driving transistor so as to calibrate the pixel circuit to account for a degradation of the pixel circuit.

51. The method according to claim 49, further comprising setting the terminal of the capacitor other than the terminal of the capacitor coupled to the node at a programming voltage during the pre-charge cycle.