Package substrate with testing pads on fine pitch traces
First Claim
1. A substrate comprising:
- a plurality of traces;
a solder resist layer covering the plurality of traces; and
a testing pad coupled to a trace from the plurality of traces, the testing pad configured to enable testing of the substrate in the absence of any component being mounted on the substrate, the testing pad being at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate.
1 Assignment
0 Petitions
Accused Products
Abstract
Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (μm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.
8 Citations
31 Claims
-
1. A substrate comprising:
-
a plurality of traces; a solder resist layer covering the plurality of traces; and a testing pad coupled to a trace from the plurality of traces, the testing pad configured to enable testing of the substrate in the absence of any component being mounted on the substrate, the testing pad being at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A substrate comprising:
-
a plurality of traces; a solder resist layer covering the plurality of traces; and a means for testing the substrate, the means for testing coupled to a trace from the plurality of traces, the means for testing configured to enable testing of the substrate in the absence of any component being mounted on the substrate, the means for testing being at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
-
-
23. A device comprising:
-
a chip; and a substrate coupled to the chip, the substrate comprising; a plurality of traces; a solder resist layer covering the plurality of traces; and a testing pad coupled to a trace from the plurality of traces, the testing pad configured to enable testing of the substrate, the testing pad being at least partially exposed and at least partially free of the solder resist layer when the substrate is coupled to the chip, wherein the testing pad is free of direct physical coupling with a bonding component of the chip. - View Dependent Claims (24, 25, 26, 27, 28)
-
-
29. A device comprising:
-
a chip; and a substrate coupled to the chip, the substrate comprising; a plurality of traces; a solder resist layer covering the plurality of traces; and a means for testing the substrate, the means for testing the substrate coupled to a trace from the plurality of traces, the means for testing the substrate configured to enable testing of the substrate, the means for testing the substrate being at least partially exposed and at least partially free of the solder resist layer when the substrate is coupled to the chip, wherein the means for testing the substrate is free of direct physical coupling with a bonding component of the chip. - View Dependent Claims (30, 31)
-
Specification