Signal monitoring of through-wafer vias using a multi-layer inductor

• US 9,372,208 B2
• Filed: 01/02/2014
• Issued: 06/21/2016
• Est. Priority Date: 01/02/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: DiRocco, Mark A., Peterson, Kirk D., Robson, Norman W., Stevens, Keith C.
• Primary Examiner(s): ZHU, SHENG-BAI
• Application Number:
  US14/146,162
• Publication Number:
  US 20150185273A1
• Time in Patent Office: 901 Days
• Field of Search: 257/621, 257/528, 257/E29.001, 257/E21.506, 438/109, 438/381, 438/622
• US Class Current: 1/1
• CPC Class Codes: G01R 17/00 Measuring arrangements involving comparison with a reference value, e.g. bridge
• CPC Class Codes: G01R 19/00 Arrangements for measuring currents or voltages or for indicating presence or sign thereof G01R5/00 takes precedence; for measuring bioelectric currents or voltages A61B5/24
• CPC Class Codes: G01R 31/2648 Characterising semiconductor materials testing of materials or semi-finished products G01R31/2831; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19104 on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

According to a method herein, a multi-level inductor is created around a through-silicon-via (TSV) in a semiconductor substrate. A voltage induced in the multi-level inductor by current flowing in the TSV is sensed, using a computerized device. The voltage is compared to a reference voltage, using the computerized device. An electrical signature of the TSV is determined based on the comparing the voltage to the reference voltage, using the computerized device.

Claims

1. A method of identifying failed components in an integrated circuit, comprising:

creating a multi-level coil inductor around a through-silicon-via (TSV) in a multi-layer semiconductor substrate, said TSV electrically connecting layers of said multi-layer semiconductor substrate, and said multi-level coil inductor comprising a coil having several turns around said TSV;

passing an electrical current through said TSV;

sensing a voltage induced in said multi-level coil inductor by said electrical current flowing in said TSV, using a computerized device;

comparing said voltage to a reference voltage, using said computerized device; and

identifying failure of said TSV based on said voltage not matching said reference voltage, using said computerized device.

2. The method according to claim 1, further comprising:

applying a time varying voltage to said TSV, using said computerized device.

3. The method according to claim 1, further comprising:

providing said reference voltage to a comparator, using said computerized device;

providing said voltage induced in said multi-level coil inductor to said comparator, using said computerized device; and

measuring a current at an output of said comparator, using said computerized device.

4. The method according to claim 3, further comprising:

calculating a resistance of said TSV from said voltage induced in said multi-level coil inductor and said current measured at said output of said comparator, using said computerized device.

5. The method according to claim 1, said sensing a voltage induced in said multi-level coil inductor further comprising amplifying said voltage.

6. The method according to claim 1, further comprising:

detecting one of a voltage spike, a voltage dip, a maximum voltage, and a minimum voltage, based on said comparing, using said computerized device.

7. A method of identifying failed components in an integrated circuit, comprising:

forming a wafer comprising a multi-layer silicon substrate;

forming a through-silicon-via (TSV) structure extending through multiple levels of said multi-layer silicon substrate, said TSV electrically connecting layers of said multi-layer silicon substrate;

forming a coil inductor in said multi-layer silicon substrate surrounding said TSV through multiple levels of said multi-layer silicon substrate, said coil inductor comprising a coil having several turns around said TSV;

passing an electrical current through said TSV;

determining a measured voltage induced in said coil inductor by said electrical current flowing in said TSV, using a computerized device;

comparing said measured voltage to a reference voltage, using said computerized device;

providing an output signal indicating resistance of said TSV based on said comparing said measured voltage to said reference voltage, using said computerized device; and

identifying failure of said TSV based on said resistance exceeding a reference resistance, using said computerized device.

8. The method according to claim 7, further comprising:

applying a time varying voltage to said TSV, using said computerized device.

9. The method according to claim 7, further comprising:

providing said reference voltage to a comparator, using said computerized device;

providing said measured voltage to said comparator, using said computerized device; and

measuring a current at an output of said comparator, using said computerized device.

10. The method according to claim 9, further comprising:

calculating said resistance of said TSV from said measured voltage and said current measured at said output of said comparator, using said computerized device.

11. The method according to claim 7, said determining a measured voltage induced in said coil inductor further comprising amplifying said measured voltage.

12. The method according to claim 7, further comprising:

detecting one of a voltage spike, a voltage dip, a maximum voltage, and a minimum voltage, based on said output signal, using said computerized device.

13. A method of identifying failed components in an integrated circuit, comprising:

forming a through-silicon-via (TSV) through multiple levels of a multi-layer substrate, said TSV electrically connecting layers of said multi-layer substrate;

surrounding said TSV with a coil inductor through multiple levels of said multi-layer substrate, said coil inductor comprising a coil having several turns around said TSV;

detecting current flowing in said TSV and measuring voltage induced in said coil inductor by said current, using a computerized device;

providing an output signal indicating resistance of said TSV based on said voltage, using said computerized device; and

identifying failure of said TSV based on said resistance exceeding a reference resistance, using said computerized device.

14. The method according to claim 13, further comprising:

comparing measured voltage induced in said coil inductor to a reference voltage, using said computerized device, said output signal being based on said comparing said measured voltage to said reference voltage.

15. The method according to claim 14, further comprising:

providing said reference voltage to a comparator, using said computerized device;

providing said measured voltage from said coil inductor to said comparator, using said computerized device; and

measuring a current at an output of said comparator, using said computerized device.

16. The method according to claim 15, further comprising:

calculating a resistance of said TSV from said voltage induced in said coil inductor and said current measured at said output of said comparator, using said computerized device.

17. The method according to claim 13, further comprising:

applying a time varying voltage to said TSV, using said computerized device.

18. The method according to claim 13, said measuring said voltage induced in said coil inductor further comprising amplifying said voltage.

19. The method according to claim 13, further comprising:

detecting one of a voltage spike, a voltage dip, a maximum voltage, and a minimum voltage, based on said output signal, using said computerized device.