Dynamically modifying a power/performance tradeoff based on processor utilization

• US 9,372,524 B2
• Filed: 12/15/2011
• Issued: 06/21/2016
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sistla, Krishnakanth V., Rowland, Mark, Varma, Ankush, Steiner, Ian M., Bace, Matthew, Borkowski, Daniel, Garg, Vivek, Akturan, Cagdas, Ananthakrishnan, Avinash N.
• Primary Examiner(s): Elamin, M
• Application Number:
  US13/326,605
• Publication Number:
  US 20120144217A1
• Time in Patent Office: 1,650 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a plurality of cores and a power controller, the power controller including a logic having circuitry to dynamically update a power management policy for a system including the processor from a power saving biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level, wherein the logic is to dynamically tune a loadline from the power saving biased policy to the performance biased policy when a ratio of a duration of a maximum performance state residency of the plurality of cores during an evaluation interval to a duration of an active state residency of the plurality of cores during the evaluation interval exceeds the threshold level.

2. The processor of claim 1, wherein a user is to select the power saving biased policy from a plurality of possible power saving biased policies.

3. The processor of claim 2, wherein the processor is to dynamically and automatically switch from the selected power saving biased policy to the performance biased policy when the utilization exceeds the threshold level.

4. The processor of claim 3, wherein the processor is to dynamically and automatically switch from the performance biased policy to the selected power saving biased policy when the utilization is less than a second threshold level, the second threshold level less than the threshold level.

5. The processor of claim 1, wherein the logic includes a dynamic loadline tuning circuit comprising:

a maximum performance accumulator to accumulate the maximum performance state residency during the evaluation interval;

an active state accumulator to accumulate the active state residency during the evaluation interval; and

an accumulator sampler to sample the maximum performance accumulator and the active state accumulator.

6. The processor of claim 5, wherein the dynamic loadline tuning circuit further comprises:

a comparator to compare the ratio to at least one of the threshold level and a second threshold level.

7. The processor of claim 6, wherein the dynamic loadline tuning circuit is to update the power management policy to the performance biased policy when the ratio is greater than the threshold level.

8. The processor of claim 5, further comprising a first active state mask to store a state of the plurality of cores at a first time period and a second active state mask to store a state of the plurality of cores at a second time period, and wherein the active state accumulator is to accumulate the active state residency based at least in part on the first and second active state masks and time stamps each associated with one of the plurality of cores and a current time stamp.

9. A method comprising:

determining, in a circuit of a power controller of a multicore processor, an active state residency for a plurality of cores of the multicore processor during an evaluation interval;

determining, in the circuit, a maximum performance state residency for the plurality of cores during the evaluation interval;

determining, in the circuit, a ratio between the maximum performance state residency and the active state residency; and

setting a power management policy based at least in part on the ratio.

10. The method of claim 9, further comprising if the ratio is greater than a high threshold, setting the power management policy to a performance policy.

11. The method of claim 10, further comprising if the ratio is less than a low threshold, setting the power management policy to a power saving policy.

12. The method of claim 11, further comprising if the ratio is between the high and low thresholds, maintaining a current power management policy.

13. The method of claim 11, further comprising dynamically updating the power management policy from the power saving policy to the performance policy when a utilization of the multicore processor exceeds a threshold.

14. The method of claim 13, further comprising dynamically updating the power management policy automatically via a logic of a power controller of the multicore processor.

15. A system comprising:

a multicore processor including a plurality of cores and a power controller including a logic having circuitry to dynamically switch a power management policy for the multicore processor from a power biased policy to a performance biased policy when a utilization of the multicore processor exceeds a threshold level, wherein the logic is to determine an active state residency for the plurality of cores and a maximum performance state residency for the plurality of cores during an evaluation interval, compare the maximum performance state residency to the active state residency, and dynamically switch the power management policy based at least in part on the comparison; and

a dynamic random access memory (DRAM) coupled to the multicore processor.

16. The system of claim 15, wherein the logic is to store a first active state mask to identify a state of the plurality of cores at a first time and a second active state mask to identify a state of the plurality of cores at a second time, and wherein the logic is to determine the active state residency based at least in part on the first and second active state masks, time stamps each associated with one of the plurality of cores and a current time stamp.

17. The system of claim 16, wherein the logic is to store a first performance state mask to identify a performance state of the plurality of cores at the first time and a second performance state mask to identify a performance state of the plurality of cores at the second time, and wherein the logic is to determine the maximum performance state residency based at least in part on the first and second performance state masks, the time stamps and the current time stamp.

18. The system of claim 15, wherein the logic is to accumulate the active state residency and the maximum performance state residency for a plurality of evaluation intervals to obtain an average active state residency and an average maximum performance state residency, to determine a ratio between the average maximum performance state residency and the average active state residency, and to dynamically switch the power management policy based at least in part on the ratio.