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Interruption of chip component managing tasks

  • US 9,372,717 B2
  • Filed: 05/08/2014
  • Issued: 06/21/2016
  • Est. Priority Date: 05/14/2013
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a processor; and

    a computer readable storage medium having computer usable program code embodied therewith, the computer usable program code executable by the processor to cause the apparatus to;

    determine a current state value associated with a currently executing task;

    store the current state value in a register;

    determine whether a first priority of a requested task is higher than a second priority of the currently executing task;

    responsive to a determination that the first priority is higher than the second priority, evaluate the current state value stored in the register and determine a time interval since receiving a request to execute the requested task;

    in response to evaluating the current state value stored in the register as indicating interruptible or determining the time interval exceeds a threshold, interrupt the currently executing task and trigger execution of the requested task on the processor; and

    in response to evaluating the current state value stored in the register as indicating uninterruptible and the time interval does not exceed the threshold, execute the requested task in response to detection of one member selected from the group consisting of;

    detection of graceful termination of the currently executing task and detection of a change to the current state value.

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