Method and system for shutting down active core based caches

• US 9,372,803 B2
• Filed: 12/20/2012
• Issued: 06/21/2016
• Est. Priority Date: 12/20/2012
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Manne, Srilatha, Schulte, Michael, Bircher, Lloyd, Govindan, Madhu Saravana Sibi, Eckert, Yasuko
• Primary Examiner(s): Queler, Adam M
• Assistant Examiner(s): Tsang, Kenneth
• Application Number:
  US13/722,808
• Publication Number:
  US 20140181413A1
• Time in Patent Office: 1,279 Days
• Field of Search: 711/135, 711/111
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Claims

1. A system comprising:

a processing unit;

at least one memory coupled to the processing unit; and

at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of blocks includes data identified as being in a modified state;

wherein;

the modified state data is flushed by writing the data to the at least one memory based on a write back policy,

the aggressiveness of the policy is based on at least one factor,

a factor is a frequency that a core of the processing unit enters an idle state,

a threshold associated with the factor is set to a predetermined number of cores meeting the factor,

wherein the aggressiveness of the policy is proportional to a degree above which the threshold is met;

and wherein the flushing allows the at least one core to be set to a power-gated state.

2. The system of claim 1 wherein the at least one factor is the number of idle cores.

3. The system of claim 1 wherein the at least one factor is the proximity of the last cache flush.

4. The system of claim 3 wherein the proximity of the last cache flush is associated with the probability that a reduction in the number of active cores has resulted in a cache flush.

5. The system of claim 1 wherein the at least one factor is the activity of the thread associated with the data.

6. The system of claim 1 wherein the at least one factor includes which cores are idle and if the idle core is associated with the data.

7. A method of shutting down at least one active based core, the method comprising:

monitoring via a processor at least one condition of a plurality of conditions regarding the at least one active based core and modifying the aggressiveness of the data eviction policy for at least one cache associated with the at least one active based core based on the monitoring;

the data eviction policy determining when modified state data is flushed by writing the data to at least one memory associated with the at least one active based core, and

wherein;

a condition is a frequency that the at least one active core enters an idle state,

a threshold associated with the condition is set to a predetermined number of cores meeting the condition, and

the aggressiveness of the policy is proportional to a degree above which the threshold is met.

8. The method of claim 7 wherein the at least one factor is the number of idle cores related to the at least one active based core.

9. The method of claim 7 wherein the at least one factor is the proximity of the last cache flush associated with the at least one active based core.

10. The method of claim 9 wherein the proximity of the last cache flush is associated with the probability that a reduction in the number of active cores has resulted in a cache flush.

11. The method of claim 7 wherein the at least one factor is the activity of the thread associated with the data.

12. The method of claim 7 wherein the at least one factor includes which cores related to the at least one active based core are idle and if the idle core is associated with the data.

13. The method of claim 7 wherein the flush allows the processor to operate with reduced power.

14. A non-transitory computer-readable medium having processor-executable instructions stored thereon which, when executed by at least one processor, will cause the at least one processor to perform a method of shutting down at least one active based core, the method comprising:

monitoring via a processor at least one condition of a plurality of conditions regarding the at least one active based core and modifying the aggressiveness of the data eviction policy for at least one cache associated with the at least one active based core based on the monitoring;

the data eviction policy determining when modified state data is flushed by writing the data to at least one memory associated with the at least one active based core, and

wherein;

a condition is a frequency that the at least one active core enters an idle state,

a threshold associated with the condition is set to a predetermined number of cores meeting the condition, and

the aggressiveness of the policy is proportional to a degree above which the threshold is met.

15. The non-transitory computer readable medium of claim 14 wherein the at least one factor is the number of idle cores related to the at least one active based core.

16. The non-transitory computer readable medium of claim 14 wherein the at least one factor is the proximity of the last cache flush associated with the at least one active based core.

17. The non-transitory computer readable medium of claim 16 wherein the proximity of the last cache flush is associated with the probability that a reduction in the number of active cores has resulted in a cache flush.

18. The non-transitory computer readable medium of claim 14 wherein the at least one factor is the activity of the thread associated with the data.

19. The non-transitory computer readable medium of claim 14 wherein the at least one factor includes which cores related to the at least one active based core are idle and if the idle core is associated with the data.

20. The non-transitory computer readable medium of claim 14 wherein the flush allows the processor to operate with reduced power.