CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer

• US 9,373,548 B2
• Filed: 08/27/2008
• Issued: 06/21/2016
• Est. Priority Date: 09/18/2006
• Status: Active Grant

• Current Assignee: Innovative Foundry Technologies LLC
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pei, Gen, Van Meer, Johannes, Luning, Scott D.
• Primary Examiner(s): MAI, ANH D
• Application Number:
  US12/199,659
• Publication Number:
  US 20090008718A1
• Time in Patent Office: 2,855 Days
• Field of Search: 257/369, 257/E27.062, 257/351
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.

Claims

1. A CMOS circuit comprising:

a PMOS transistor having a first gate electrode;

an NMOS transistor adjacent the PMOS transistor in a channel width direction, the NMOS transistor having a second gate electrode that is spaced apart from the first gate electrode in the channel width direction and separate from the first gate electrode;

an isolation region that separates the NMOS transistor from the PMOS transistor, the isolation region having a first portion and a second portion;

a compressive stress liner overlying the first gate electrode of the PMOS transistor, not overlying the second portion of the isolation region and contacting the first portion of the isolation region; and

a tensile stress liner overlying the second gate electrode of the NMOS transistor, and contacting the second portion of the isolation region,

wherein a portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration to define an overlap region of the compressive stress liner and the tensile stress liner at which the portion of the tensile stress liner overlaps with and physically contacts the portion of the compressive stress liner to result in an enhanced transverse stress in the compressive stress liner in the channel width direction, wherein the overlap region is between the first gate electrode and the second gate electrode.

2. The CMOS circuit of claim 1, wherein the portion of the compressive stress liner is an edge portion of the compressive stress liner and wherein the portion of the tensile stress liner overlies the edge portion of the compressive stress liner.

3. The CMOS circuit of claim 1, wherein the first portion is closer to the PMOS transistor and wherein the second portion is closer to the NMOS transistor.