Semiconductor device

• US 9,373,640 B2
• Filed: 07/21/2015
• Issued: 06/21/2016
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): Tran, Thanh Y
• Application Number:
  US14/804,478
• Publication Number:
  US 20150325596A1
• Time in Patent Office: 336 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Claims

1. A semiconductor device comprising:

a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a plurality of storage elements connected in parallel between the first wiring and the second wiring,

wherein one of the plurality of storage elements includes a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and

a third transistor having a third gate electrode, a third source electrode, and a third drain electrode,

wherein the first transistor is provided in a substrate including a semiconductor material,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the first wiring and the third source electrode are electrically connected to each other,

wherein the third drain electrode and the first source electrode are electrically connected to each other,

wherein the second wiring and the first drain electrode are electrically connected to each other,

wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the fourth wiring and the second gate electrode are electrically connected to each other, and

wherein the fifth wiring and the third gate electrode are electrically connected to each other.

2. The semiconductor device according to claim 1, wherein the first transistor includes a channel region provided in the substrate including the semiconductor material, impurity regions provided so as to sandwich the channel region, a first gate insulating layer over the channel region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode electrically connected to the impurity regions.

3. The semiconductor device according to claim 1, wherein the second transistor includes the second gate electrode over the substrate including the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the third transistor includes a channel region provided in the substrate including the semiconductor material, impurity regions provided so as to sandwich the channel region, a third gate insulating layer over the channel region, the third gate electrode over the third gate insulating layer, and the third source electrode and the third drain electrode electrically connected to the impurity regions.

5. The semiconductor device according to claim 1, wherein the substrate including the semiconductor material is one of a single crystal semiconductor substrate and an SOI substrate.

6. The semiconductor device according to claim 1, wherein the semiconductor material is silicon.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor material.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a crystal of In₂Ga₂ZnO₇.

9. The semiconductor device according to claim 1, wherein concentration of hydrogen in the oxide semiconductor layer is 5×

10¹⁹/cm³ or less.

10. The semiconductor device according to claim 1, wherein an off-state current of the second transistor is 1×

10<sup>−

13</sup> A or less.

11. The semiconductor device according to claim 1,

wherein the second wiring is parallel to the third wiring, and

wherein the fourth wiring is parallel to the fifth wiring.

12. The semiconductor device according to claim 1,

wherein the second wiring is parallel to the fourth wiring, and

wherein the third wiring is parallel to the fifth wiring.

13. A semiconductor device comprising:

a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a plurality of storage elements connected in parallel between the first wiring and the second wiring,

wherein one of the plurality of storage elements includes a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor having a second gate electrode, a second source electrode, and a second drain electrode;

a third transistor having a third gate electrode, a third source electrode, and a third drain electrode; and

a capacitor,

wherein the first transistor is provided in a substrate including a semiconductor material,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other,

wherein the first wiring, the first source electrode, and the other of the electrodes of the capacitor are electrically connected to each other,

wherein the first drain electrode and the third source electrode are electrically connected to each other,

wherein the second wiring and the third drain electrode are electrically connected to each other,

wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the fourth wiring and the second gate electrode are electrically connected to each other, and

wherein the fifth wiring and the third gate electrode are electrically connected to each other.

14. The semiconductor device according to claim 13, wherein the first transistor includes a channel region provided in the substrate including the semiconductor material, impurity regions provided so as to sandwich the channel region, a first gate insulating layer over the channel region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode electrically connected to the impurity regions.

15. The semiconductor device according to claim 13, wherein the second transistor includes the second gate electrode over the substrate including the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

16. The semiconductor device according to claim 13, wherein the third transistor includes a channel region provided in the substrate including the semiconductor material, impurity regions provided so as to sandwich the channel region, a third gate insulating layer over the channel region, the third gate electrode over the third gate insulating layer, and the third source electrode and the third drain electrode electrically connected to the impurity regions.

17. The semiconductor device according to claim 13, wherein the substrate including the semiconductor material is one of a single crystal semiconductor substrate and an SOI substrate.

18. The semiconductor device according to claim 13, wherein the semiconductor material is silicon.

19. The semiconductor device according to claim 13, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor material.

20. The semiconductor device according to claim 13, wherein the oxide semiconductor layer includes a crystal of In₂Ga₂ZnO₇.

21. The semiconductor device according to claim 13, wherein concentration of hydrogen in the oxide semiconductor layer is 5×

10¹⁹/cm³ or less.

22. The semiconductor device according to claim 13, wherein an off-state current of the second transistor is 1×

10<sup>−

13</sup> A or less.