Nonplanar III-N transistors with compositionally graded semiconductor channels

• US 9,373,693 B2
• Filed: 11/06/2014
• Issued: 06/21/2016
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Then, Han Wui, Dasgupta, Sansaptak, Radosavljevic, Marko, Chu-Kung, Benjamin, Sung, Seung Hoon, Gardner, Sanaz K., Chau, Robert S.
• Primary Examiner(s): Fan, Michele
• Application Number:
  US14/535,240
• Publication Number:
  US 20150064859A1
• Time in Patent Office: 593 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02387 Group 13/15 materials
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66409 Unipolar field-effect transistors
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

Claims

1. A method of forming a III-N field effect transistor (FET) comprising a crystalline wide band gap transition layer, a III-N semiconductor channel layer formed over the crystalline wide band gap transition layer, and a wide band gap polarization layer formed over the III-N semiconductor channel layer, the method comprising:

forming the crystalline wide band gap transition layer over a substrate;

epitaxially growing the III-N semiconductor channel layer over the wide band gap transition layer, wherein the growing comprises grading the composition of the III-N semiconductor channel layer over a thickness of the channel layer toward a narrower band gap composition proximate the wide band gap polarization layer;

epitaxially growing the wide band gap polarization layer over the III-N semiconductor channel layer; and

forming a gate stack over surfaces of the III-N semiconductor channel layer between the wide band gap transition layer and the wide band gap polarization layer.

2. The method of claim 1, wherein epitaxially growing the III-N semiconductor channel layer comprises grading the composition of the III-N semiconductor channel layer symmetrically about a half thickness of the III-N semiconductor channel layer.

3. The method of claim 1, wherein epitaxially growing the III-N semiconductor channel layer comprises grading the composition of the III-N semiconductor channel layer from a first higher indium content and a monotonically decreasing indium content.

4. The method of claim 1, wherein epitaxially growing the III-N semiconductor channel layer comprises grading the composition of the III-N semiconductor channel layer from a first higher aluminum content proximate to the wide band gap transition layer with monotonically decreasing aluminum content toward the narrowest band gap composition.

5. The method of claim 4, wherein epitaxially growing the III-N semiconductor channel layer comprises grading the composition of the III-N semiconductor channel layer from AlGaN with at least 30% Al proximate the wide band gap transition layer to GaN at the narrowest band gap composition, and then returning to AlGaN with at least 30% Al proximate the wide band gap polarization layer.

6. The method of claim 1, wherein forming the gate stack further comprises:

depositing one or more gate dielectric layer over two or more {1010} surfaces of the of the III-N semiconductor channel layer using an atomic layer deposition process; and

depositing one or more gate electrode layer over the gate dielectric layer.