Multiple-gate semiconductor device and method

• US 9,373,704 B2
• Filed: 11/24/2014
• Issued: 06/21/2016
• Est. Priority Date: 12/02/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Tung Ying, Weng, Li-Wen, Chan, Chien-Tai, Lin, Da-Wen, Lin, Hsien-Chin
• Primary Examiner(s): SANDVIK, BENJAMIN P
• Application Number:
  US14/552,237
• Publication Number:
  US 20150079753A1
• Time in Patent Office: 575 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a plurality of fins in a substrate;

forming first isolation regions in the substrate, the first isolation regions extending a first depth from a surface of the substrate;

forming second isolation regions in the substrate, the second isolation regions extending a second depth from the surface of the substrate, the second depth being less than the first depth;

after forming the first isolation regions and the second isolation regions, removing a portion of each of the plurality of fins and the second isolation regions; and

forming a source/drain region, the source/drain region connecting the plurality of fins.

2. The method of claim 1, wherein the forming the source/drain region is done at least in part through an epitaxial growth process.

3. The method of claim 2, further comprising forming a contact etch stop layer over the source/drain region.

4. The method of claim 3, further comprising forming a silicide at least partially from the source/drain region prior to forming the contact etch stop layer.

5. The method of claim 1, wherein the removing the portion of each of the plurality of fins and the second isolation regions further comprises recessing a portion of the first isolation regions.

6. The method of claim 5, further comprising forming spacers in contact with the portion of the first isolation regions.

7. The method of claim 1, wherein the plurality of fins has a pitch of between about 30 nm and about 150 nm.

8. A method of forming a semiconductor device, the method comprising:

forming a first isolation region in a substrate between a first fin and a second fin;

forming a second isolation region in the substrate on an opposite side of the first fin from the first isolation region, wherein the second isolation region extends further into the substrate than the first isolation region;

removing a first portion of the first fin and a an exposed second portion of the second fin, wherein the removing the first portion of the first fin continues until the first portion of the first fin is below a top surface of the first isolation region; and

growing a continuous source/drain region extending from the first fin to the second fin.

9. The method of claim 8, wherein the first fin and the second fin have a pitch of between about 20 nm and about 150 nm.

10. The method of claim 8, further comprising depositing a contact etch stop layer over the continuous source/drain region.

11. The method of claim 8, wherein the removing the first portion of the first fin further comprises recessing a portion of the second isolation region.

12. The method of claim 11, further comprising forming spacers in contact with the second isolation regions.

13. The method of claim 8, wherein the growing the continuous source/drain region further comprises epitaxially growing the source/drain region to extend over the second isolation region.

14. The method of claim 8, further comprising growing a silicide on the continuous source/drain region.

15. A method of forming a semiconductor device, the method comprising:

depositing dielectric material into a first opening and a second opening of a substrate, wherein the first opening is located between a first fin and a second fin and wherein the second opening is not located between the first fin and the second fin, the first opening extending into the substrate less than the second opening;

recessing the dielectric material such that sidewalls of the first fin and the second fin are exposed;

removing the dielectric material from a first region in the first opening exposed by a dielectric layer; and

growing a source/drain region within the first region, the source/drain region extending between the first fin and the second fin.

16. The method of claim 15, wherein the growing the source/drain region is done at least in part through an epitaxial growth process.

17. The method of claim 15, further comprising forming a contact etch stop layer over the source/drain region.

18. The method of claim 17, further comprising forming a silicide at least in part from the source/drain region prior to the forming the contact etch stop layer.

19. The method of claim 15, further comprising forming spacers in contact with the dielectric material after the growing the source/drain region.

20. The method of claim 15, wherein the removing the dielectric material from a first region exposed by a gate stack further removes the dielectric material from a second region in the second opening exposed by the gate stack.