CMOS integrated method for the release of thermopile pixel on a substrate by using anisotropic and isotropic etching

• US 9,373,772 B2
• Filed: 01/15/2014
• Issued: 06/21/2016
• Est. Priority Date: 01/15/2014
• Status: Active Grant

• Current Assignee: Excelitas Singapore Pte., Ltd., Excelitas Technologies Singapore Pte., Ltd.
• Original Assignee: Excelitas Technologies Singapore Pte., Ltd.
• Inventors: Huminic, Grigore D., Vasseur, Philippe, Karagoezoglu, Hermann, Marinescu, Radu M.
• Primary Examiner(s): Sarkar, Asok K
• Assistant Examiner(s): Yemelyanov, Dmitriy
• Application Number:
  US14/155,910
• Publication Number:
  US 20150200347A1
• Time in Patent Office: 888 Days
• Field of Search: 438/54
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14649 Infrared imagers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H10N 10/01 Manufacture or treatment

Abstract

A method for manufacturing an imaging device is presented. The method starts with providing a wafer having a membrane with an opening bonded to a substrate. A photoresist layer is deposited over the membrane and wafer surface. A portion of the substrate back surface under a central part of the membrane is etched anisotropicly. A first region of the photoresist layer is removed, exposing an opening in the membrane, so that a first isotropic etching of the substrate is performed through the membrane opening. A second region of the photoresist layer is stripped, exposing a second membrane opening, providing access for a second isotropic etching of the substrate through the first and/or second membrane opening.

Claims

1. A method for manufacturing an imaging device, comprising the steps of:

providing a wafer comprising a first layer, a second layer, and a third layer, the second layer having a front surface adjacent to the first layer and a back surface adjacent to the third layer, the first layer having a pair of inner openings therethrough;

anisotropic etching of a portion of the second layer back surface beneath a central part of the first layer to form a cavity between the pair of inner openings, the pair of inner openings not extending into the cavity; and

performing a first isotropic etching of a first portion of the second layer front surface through the pair of inner openings to form cavity extensions such that the pair of inner openings provide a channel from a top side of the wafer through the first layer into the cavity.

2. The method of claim 1, wherein the first layer comprises a membrane and a thermopile structure.

3. The method of claim 2, wherein the second layer comprises a semiconductor substrate.

4. The method of claim 3, wherein the semiconductor substrate comprises one or more of the group consisting of silicon, germanium, silicon germanium, and gallium arsenide.

5. The method of claim 1, wherein the anisotropic etching penetrates through substantially a whole thickness of the second layer.

6. The method of claim 5, wherein the anisotropic etching is performed through an opening of the third layer aligned with the pair of inner openings opening of the first layer and CMOS structures of the second layer.

7. The method of claim 5, wherein the second layer is between 50 and 600 μ

m thick.

8. The method of claim 1, further comprising the step of performing a second isotropic etching of a second portion of the of the second layer front surface through the first layer pair of inner openings and/or a first layer pair of outer openings.

9. The method of claim 8, wherein:

the first and/or second isotropic etching is aligned with a front surface pattern.

10. The method of claim 1, further comprising the steps of:

removing a first mask from the first layer; and

removing a second mask from the first layer.

11. The method of claim 10, wherein the first mask and/or the second mask comprises a photoresist.

12. The method of claim 10, wherein the first mask and/or the second mask comprises a metal mask.

13. A method for manufacturing an imaging device, comprising the steps of:

first providing a wafer comprising a substrate having a first surface and a second surface opposite the first surface, and a membrane attached to the first surface, wherein the membrane includes an opening exposing the first surface;

subsequently, depositing a photoresist layer over the membrane and wafer first surface;

after depositing the photoresist layer, masking a portion of the photoresist layer to form a first region and a second region;

subsequently, anisotropic etching a portion of the substrate second surface under a central part of the membrane;

after the anisotropic etching, removing the first region of the photoresist layer;

subsequently, performing a first isotropic etching of the substrate through the membrane opening;

after the first isotropic etching, stripping the second region of the photoresist layer; and

subsequently, performing a second isotropic etching of the substrate through the membrane opening.

14. The method of claim 13, wherein the anisotropic etching comprises DRIE.

15. The method of claim 13, wherein the anisotropic etching penetrates through substantially the whole thickness of the substrate.

16. The method of claim 13, wherein the substrate comprises one or more of the group consisting of silicon, germanium, silicon germanium, and gallium arsenide.

17. The method of claim 13, wherein the step of providing a wafer further comprises the steps of:

depositing of a dielectric layer on the wafer first surface; and

depositing a backside mask to the wafer second surface.

18. The method of claim 17, wherein the anisotropic etching is performed through an opening in the backside mask located under a central part of the membrane.

19. The method of claim 17, wherein the backside mask is selected from the group consisting of a metal mask, a photoresist mask, and a dielectric mask.

20. A method for manufacturing an imaging device, comprising the steps of:

providing a wafer comprising a first layer, a second layer, and a third layer, the second layer having a front surface adjacent to the first layer and a back surface adjacent to the third layer, the first layer having a pair of inner openings therethrough;

anisotropic etching of a portion of the second layer back surface beneath a central part of the first layer to form a cavity between the pair of inner openings, the pair of inner openings not extending into the cavity, the first layer acting as an etch stop to the anisotropic etching such that the anisotropic etching only etches the entire thickness of the second layer up to the first layer; and

performing a first isotropic etching of a first portion of the second layer front surface through the pair of inner openings to form cavity extensions such that the pair of inner openings provide a channel from a top side of the wager through the first layer into the cavity.

21. A method for manufacturing an imaging device, comprising the steps of:

providing a wafer comprising a first layer, a second layer, a third layer, a CMOS structure, and a photoresist layer, the second layer having a front surface adjacent to the first layer and a back surface adjacent to the third layer, the first layer having a pair of inner openings therethrough and a pair of outer openings therethrough, the at least one CMOS structure disposed on an outer portion of the wafer relative to the pair of outer openings, the photoresist layer disposed on a front surface of the first layer so as to cover at least the pair of outer openings and the CMOS structure;

anisotropic etching of a portion of the second layer back surface beneath a central part of the first layer between the pair of inner openings, the first layer acting as an etch stop layer, to form a cavity in the second layer between the pair of inner openings; and

performing a first isotropic etching of a first portion of the second layer front surface through the pair of inner openings to form first cavity extensions primarily undercutting inwards away from the pair of outer openings and the CMOS structure.

22. The method of claim 21, wherein forming the cavity in the second layer between the pair of inner openings, and providing the photoresist layer so as to cover at least the pair of outer openings and the CMOS structure, and subsequently performing the isotropic etching through the pair of inner openings, controls an outward undercut near the CMOS structure.

23. The method of claim 21, wherein the first cavity extensions are disposed a distance away from the CMOS structure towards an inner portion of the wafer.

24. The method of claim 21, further comprising, after performing the first isotropic etching, removing the photoresist layer and performing a second isotropic etching through the outer openings and/or inner openings to form second cavity extensions.

25. The method of claim 23, wherein the first and second cavity extensions are disposed a distance away from the CMOS structure towards an inner portion of the wafer.