Signal processing

• US 9,374,069 B2
• Filed: 07/25/2014
• Issued: 06/21/2016
• Est. Priority Date: 07/26/2013
• Status: Active Grant

• Current Assignee: Atlantic Inertial Systems Incorporated (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: Atlantic Inertial Systems Incorporated (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Townsend, Kevin
• Primary Examiner(s): COX, CASSANDRA F
• Application Number:
  US14/341,216
• Publication Number:
  US 20160028380A1
• Time in Patent Office: 697 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G01C 19/5684 the devices involving a micromechanical structure
• CPC Class Codes: G01C 19/5776 Signal processing not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
• CPC Class Codes: H03D 1/18 of semiconductor devices
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 3/30 Delta-sigma modulation

Abstract

A method of processing an amplitude-modulated analog signal at a carrier frequency F_c comprises: digitizing the analog signal to produce an input bit stream that represents the amplitude of the analog signal; generating an in-phase reference bit stream that is synchronous to the carrier frequency F_c and represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and multiplying the input bit stream with the in-phase reference bit stream to produce an output bit stream representing the amplitude modulation of the analog signal.

Claims

1. A method of processing an amplitude-modulated analog signal at a carrier frequency F_c, comprising:

digitizing the analog signal at a sampling rate R that is synchronous to the carrier frequency F_c to produce an input bit stream that represents the amplitude of the analog signal, wherein R=2*(1*3*5 . . . N)*F_c or R=4*(1*3*5 . . . N)*F_c, where N>

1 is an odd number representing odd harmonics in the analog signal;

generating an in-phase reference bit stream that is synchronous to the carrier frequency F_c and represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and

multiplying the input bit stream with the in-phase reference bit stream to produce an output bit stream representing the amplitude modulation of the analog signal.

2. The method of claim 1, comprising digitizing the analog signal at a sampling rate R=4*3*F_c=12F_c or R=4*3*5*F_c=60F_c.

3. The method of claim 1, wherein digitizing the analog signal is performed using pulse-density modulation (PDM) or pulse-width modulation (PWM).

4. The method of claim 1, wherein digitizing the analog signal comprises carrying out delta-sigma modulation to produce a one-bit input bit stream.

5. The method of claim 1, wherein digitizing the analog signal is performed using pulse-code modulation (PCM).

6. The method of claim 1, wherein digitizing the analog signal comprises carrying out multi-bit conversion to produce a multi-bit input bit stream.

7. The method of claim 1, comprising generating a multi-bit in-phase reference bit stream that is synchronous to the carrier frequency F_c.

8. The method of claim 1, further comprising:

generating a quadrature reference bit stream that is synchronous to the carrier frequency F_c and represents a quadrature digital reference signal substantially in the form of a cosine and/or sine wave; and

multiplying the input bit stream with the quadrature reference bit stream to produce an output bit stream representing a quadrature component of the analog signal.

9. The method of claim 8, comprising generating a pair of synchronous in-phase and quadrature reference bit streams.

10. The method of claim 1, wherein generating an in-phase reference bit stream that is synchronous to the carrier frequency F_c comprises controlling a clock so as to skew the timing to achieve phase accuracy.

11. A pickoff signal processing system for a sensor comprising a movement sensing structure, the system comprising:

an analog-to-digital converter (ADC) arranged to digitize an amplitude-modulated analog pickoff signal representing movement of the sensing structure which is at a carrier frequency F_c and produce an input bit stream that represents the amplitude of the analog pickoff signal, wherein the ADC is arranged to digitize the analog pickoff signal at a sampling rate R that is synchronous to the carrier frequency F_c according to R=2*(1*3*5 . . . N)*F_c or R=4*(1*3*5 . . . N)*F_c, where N>

1 is an odd number representing odd harmonics in the analog signal;

a synchronous modulator or look-up table arranged to generate an in-phase reference bit stream that is synchronous to the carrier frequency F_c and represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and

logic means arranged to multiply the input bit stream with the in-phase reference bit stream and produce an output bit stream representing the amplitude modulation of the analog pickoff signal.

12. The system of claim 11, wherein the ADC is arranged to digitize the analog pickoff signal at a sampling rate R=4*3*F_c=12F_c or R=4*3*5*F_c=60F_c.

13. The system of claim 11, wherein the ADC is arranged to digitize the analog pickoff signal using pulse-density modulation (PDM), or pulse-width modulation (PWM), or pulse-code modulation (PCM).

14. The system of claim 11, wherein the ADC is arranged to carry out delta-sigma modulation to produce a one-bit input bit stream.

15. The system of claim 11, wherein the ADC is arranged to carry out multi-bit conversion to produce a multi-bit input bit stream.

16. The system of claim 11, wherein:

the synchronous modulator or look-up table is arranged to generate a quadrature reference bit stream that is synchronous to the carrier frequency F_c and represents a quadrature digital reference signal substantially in the form of a cosine and/or sine wave; and

the logic means is arranged to multiply the input bit stream with the quadrature reference bit stream to produce an output bit stream representing a quadrature component of the analog signal.

17. The system of claim 16, wherein the synchronous modulator or look-up table is arranged to generate a synchronous pair of in-phase and quadrature reference bit streams.

18. The system of claim 11, wherein the synchronous modulator or look-up table utilizes a clock controlled relative to the ADC so as to skew the timing to achieve phase accuracy.