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Capacitively coupled input buffer

  • US 9,374,093 B2
  • Filed: 01/10/2014
  • Issued: 06/21/2016
  • Est. Priority Date: 01/10/2014
  • Status: Active Grant
First Claim
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1. A buffer circuit comprising:

  • a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal;

    a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage, the first buffer stage comprising a data hold time; and

    ,a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse within the data hold time of the first buffer stage such that the second terminal of the capacitor is restored to a level corresponding to a level of the input signal during the data hold time.

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