Capacitively coupled input buffer

• US 9,374,093 B2
• Filed: 01/10/2014
• Issued: 06/21/2016
• Est. Priority Date: 01/10/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Pelley, Perry H., Ramaraju, Ravindraraj
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): SKIBINSKI, THOMAS S
• Application Number:
  US14/152,177
• Publication Number:
  US 20150200650A1
• Time in Patent Office: 893 Days
• Field of Search: 327108-112, 327178-180, 327/205, 327/206, 327/185, 327198-203, 327/208, 327210-212, 327/214, 327/261, 327/263, 327/264, 327/268, 327276-278, 327/284, 327/285, 327291-294, 327/299, 327306-333, 327374-391, 327530-550, 327/427, 327/434, 327/437, 326/82, 326/83, 326/87
• US Class Current: 1/1
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time.

Claims

1. A buffer circuit comprising:

a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal;

a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage, the first buffer stage comprising a data hold time; and

,

a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse within the data hold time of the first buffer stage such that the second terminal of the capacitor is restored to a level corresponding to a level of the input signal during the data hold time.

2. The buffer circuit of claim 1 wherein:

the first buffer stage comprises a first transistor and a second transistor, the control pulse of the pulse generator being coupled to a gate of the first transistor, an inverse of the control pulse being coupled to a gate of the second transistor such that only one of the first transistor and the second transistor are on during a particular hold time.

3. The buffer circuit of claim 2 wherein:

the first buffer stage comprises a first logic gate and a second logic gate, the first logic gate and the second logic gate each receiving the control pulse of the pulse generator, an output of the first logic gate coupled to the gate of the first transistor and coupling the control pulse to the gate of the first transistor and an output of the second logic gate coupled to the gate of the second transistor and coupling an inverse of the control pulse to the gate of the second transistor.

4. The buffer circuit of claim 1 further comprising:

a second capacitor coupled between the second terminal of the capacitor and ground, the capacitor and the second capacitor providing a voltage divider, the voltage divider dividing a larger input signal voltage down to an internal supply voltage range.

5. A buffer circuit comprising:

a first buffer stage coupled to receive an input signal and a first reference voltage and a second reference voltage, the first buffer stage enabling the buffer circuit to have independently settable high and low input thresholds based upon the first reference voltage and the second reference voltage.

6. The buffer circuit of claim 5 wherein:

the first buffer stage comprises a first transistor and a second transistor, the input signal being provided to a control terminal of the first transistor and a control terminal of the second transistor;

the first reference voltage being provided to a first current handling terminal of the first transistor, the second reference voltage being provided to a first current handling terminal of the second transistor.

7. The buffer circuit of claim 5 wherein:

the first buffer stage comprises a third transistor and a fourth transistor,

a second current handling terminal of the first transistor being coupled to a first current handling terminal of the third transistor;

a second current handling terminal of the second transistor being coupled to a first current handling terminal of the fourth transistor;

a second current handling terminal of the third transistor and a second current handling terminal of the fourth transistor being coupled together to provide an output of the first buffer stage.

8. The buffer circuit of claim 7 wherein:

the first buffer stage comprises a first logic gate and a second logic gate, an output of the first logic gate coupled to a gate of the third transistor and providing a third transistor control signal to the gate of the third transistor and an output of the second logic gate coupled to a gate of the fourth transistor and providing a fourth transistor control signal to the gate of the fourth transistor.

9. The buffer circuit of claim 8 wherein:

the buffer circuit further comprises a second buffer stage, the second buffer stage comprising a latch, the latch latching a threshold calibrated input signal to prevent coupling to a calibrated input signal.

10. The buffer circuit of claim 8 wherein:

the first and second logic gates each receive a clock signal.

11. A method comprising:

receiving an input signal at a first terminal of a capacitor, the capacitor comprising the first terminal and a second terminal;

providing a capacitive input signal to a first buffer stage coupled from a second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage, the first buffer stage comprising a data hold time;

generating a control pulse within the data hold time of the first buffer stage; and

,

controlling the first buffer stage via the control pulse such that the second terminal of the capacitor is restored to a level corresponding to a level of the input signal during the data hold time.

12. The method of claim 11 wherein:

the first buffer stage comprises a first transistor and a second transistor, the control pulse being coupled to a gate of the first transistor, an inverse of the control pulse being coupled to a gate of the second transistor such that only one of the first transistor and the second transistor are on during a particular hold time.

13. The method of claim 12 wherein:

the first buffer stage comprises a first logic gate and a second logic gate, the first logic gate and the second logic gate each receiving the control pulse, an output of the first logic gate coupled to the gate of the first transistor and coupling the control pulse to the gate of the first transistor and an output of the second logic gate coupled to the gate of the second transistor and coupling inverse of the control pulse to the gate of the second transistor.

14. The method of claim 11 wherein:

a second capacitor is coupled between the second terminal of the capacitor and ground, the capacitor and the second capacitor providing a voltage divider, the voltage divider dividing a larger input signal voltage down to an internal supply voltage range.

15. A method comprising:

receiving an input signal at a first buffer stage of a buffer; and

,

receiving a first reference voltage and a second reference voltage, the first buffer stage enabling the buffer to have independently settable high and low input thresholds based upon the first reference voltage and the second reference voltage.

16. The method of claim 15 wherein:

the first buffer stage comprises a first transistor and a second transistor, the input signal being provided to a control terminal of the first transistor and a control terminal of the second transistor;

the first reference voltage being provided to a first current handling terminal of the first transistor, the second reference voltage being provided to a first current handling terminal of the second transistor.

17. The method of claim 16 wherein:

the first buffer stage comprises a third transistor and a fourth transistor,

a second current handling terminal of the first transistor is coupled to a first current handling terminal of the third transistor;

a second current handling terminal of the second transistor is coupled to a first current handling terminal of the fourth transistor;

a second current handling terminal of the third transistor and a second current handling terminal of the fourth transistor are coupled together to provide an output of the first buffer stage.

18. The method of claim 17 wherein:

the first buffer stage comprises a first logic gate and a second logic gate, an output of the first logic gate coupled to a gate of the third transistor and providing a third transistor control signal to the gate of the third transistor and an output of the second logic gate coupled to a gate of the fourth transistor and providing a fourth transistor control signal to the gate of the fourth transistor.

19. The method of claim 18 wherein:

the buffer circuit further comprises a second buffer stage, the second buffer stage comprising a latch, the latch latching a threshold calibrated input signal to prevent coupling to a calibrated input signal.

20. The buffer circuit of claim 18 wherein:

the first and second logic gates each receive a clock signal.