Multi-wire open-drain link with data symbol transition based clocking

• US 9,374,216 B2
• Filed: 03/19/2014
• Issued: 06/21/2016
• Est. Priority Date: 03/20/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sengoku, Shoichiro, Cheung, Joseph, Wiley, George Alan
• Primary Examiner(s): Washburn, Daniel
• Assistant Examiner(s): HUGHES, EBONI N
• Application Number:
  US14/220,056
• Publication Number:
  US 20140286466A1
• Time in Patent Office: 825 Days
• Field of Search: 375/295, 375/316, 375/354, 327/153, 327/155, 327/158, 327/161, 327172-176, 327/215, 327/217, 327/218, 327/284, 327/291, 327/298, 327/299
• US Class Current: 1/1
• CPC Class Codes: H03K 19/00 Logic circuits, i.e. having at least two inputs acting on one output circuits for computer systems using fuzzy logic G06N7/02; Inverting circuits
• CPC Class Codes: H03K 2005/00293 Output pulse is a delayed pulse issued after a rising or a falling edge, the length of the output pulse not being in relation with the length of the input triggering pulse
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/134 with field-effect transistors
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence
• CPC Class Codes: H03K 5/153 Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant switching at zero crossing H03K17/13
• CPC Class Codes: H03K 5/1534 Transition or edge detectors
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

Claims

1. A method for generating a clock signal, comprising:

receiving one or more signals from a multi-wire communication interface, wherein a sequence of symbols is encoded in the one or more signals;

determining a first transition in the one or more signals, wherein the first transition comprises a rising edge;

generating a first clock pulse on the clock signal responsive to the first transition and after a preconfigured first interval provided by delaying the first clock pulse using a first delay circuit;

determining a second transition in the one or more signals, wherein the second transition comprises a falling edge; and

generating a second clock pulse on the clock signal responsive to the second transition and after a preconfigured second interval provided by delaying the second clock pulse using a second delay circuit,

wherein the preconfigured first interval and the preconfigured second interval have different durations.

2. The method of claim 1, wherein the preconfigured first and/or second intervals are selected to cause the clock pulse to occur when a symbol is transmitted on the communication interface, thereby permitting the symbol to be reliably sampled.

3. The method of claim 1, wherein the preconfigured first and/or second intervals are configured based on a rise time and a fall time associated with the communication interface, and the rise time corresponds to a rise time associated with an open-drain transistor.

4. The method of claim 3, wherein the preconfigured second interval is selected to match a first delay that is associated with the rise time.

5. The method of claim 4, wherein the preconfigured first interval is selected to match a second delay that is associated with the fall time.

6. The method of claim 1, further comprising aggregating the first clock pulse with at least one additional clock pulse generated in response to the first transition.

7. The method of claim 1, further comprising calibrating the preconfigured first and/or second intervals.

8. The method of claim 1, further comprising:

providing a rising calibration transition on the communication interface;

measuring a first delay associated with a first calibration clock pulse generated from the rising calibration transition;

providing a falling calibration transition on the communication interface;

measuring a second delay associated with a second calibration clock pulse generated from the falling calibration transition; and

modifying at least one preconfigured interval by an amount calculated to minimize a difference between the first delay and the second delay.

9. The method of claim 8, wherein modifying the at least one preconfigured interval comprises:

adjusting a programmed delay of the first delay circuit based on a measured delay associated with the first calibration clock pulse; and

adjusting a programmed delay of the second delay circuit based on a measured delay associated with the second calibration clock pulse.

10. The method of claim 8, wherein modifying the at least one preconfigured interval comprises:

using a timer that reflects a desired delay associated with the first calibration clock pulse and the second calibration clock pulse.

11. An apparatus for generating a clock signal, comprising:

means for receiving one or more signals from a multi-wire communication interface, wherein a sequence of symbols is encoded in the one or more signals;

means for determining a first transition in the one or more signals, wherein the first transition comprises a rising edge;

means for generating a first clock pulse on the clock signal responsive to the first transition and after a preconfigured first interval;

means for delaying the first clock pulse by the preconfigured first interval, the means for delaying the first clock pulse including a first delay circuit;

means for determining a second transition in the one or more signals, wherein the second transition comprises a falling edge;

means for generating a second clock pulse on the clock signal responsive to the second transition and after a preconfigured second interval; and

means for delaying the second clock pulse by the preconfigured second interval, the means for delaying the second clock pulse including a second delay circuit,

wherein the preconfigured first interval and the preconfigured second interval have different durations.

12. The apparatus of claim 11, wherein the preconfigured first and/or second intervals are selected to cause the clock pulse to occur when a symbol is transmitted on the communication interface, thereby permitting the symbol to be reliably sampled.

13. The apparatus of claim 11, wherein the preconfigured first and/or second intervals are configured based on a rise time and a fall time associated with the communication interface, and the rise time corresponds to a rise time associated with an open-drain transistor.

14. The apparatus of claim 13, wherein the preconfigured second interval is selected to match a first delay that is associated with the rise time.

15. The apparatus of claim 14, wherein the preconfigured first interval is selected to match a second delay that is associated with the fall time.

16. The apparatus of claim 11, further comprising means for aggregating the first clock pulse with at least one additional clock pulse generated in response to the first transition.

17. The apparatus of claim 11, further comprising means for calibrating the preconfigured first and/or second intervals.

18. The apparatus of claim 17, wherein the means for calibrating the preconfigured first and/or second intervals is configured to:

respond to first and second calibration transitions that are in different directions from one another by measuring respective delays associated with clock pulses generated for the first and second calibration transitions, and modify the preconfigured first and/or second intervals to minimize a difference in the respective delays.

19. The apparatus of claim 18, wherein the means for calibrating the preconfigured first and/or second intervals adjusts a programmed delay of the first delay circuit based on a measured delay associated with a first calibration clock pulse, and adjusts a programmed delay of the second delay circuit based on a measured delay associated with a second calibration clock pulse.

20. The apparatus of claim 18, wherein the respective delays are measured using a timer that reflects a desired delay associated with a first calibration clock pulse and a second calibration clock pulse.

21. An apparatus for generating a clock signal, comprising:

a processing system configured to;

receive one or more signals from a multi-wire communication interface, wherein a sequence of symbols is encoded in the one or more signals;

determine a first transition in the one or more signals, wherein the first transition comprises a rising edge;

generate a first clock pulse on the clock signal responsive to the first transition after a preconfigured first interval provided by delaying the first clock pulse using a first delay circuit; and

determine a second transition in the one or more signals, wherein the second transition comprises a falling edge

generate a second clock pulse on the clock signal responsive to the second transition after a preconfigured second interval provided by delaying the second clock pulse using a second delay circuit,

wherein the preconfigured first interval and the preconfigured second interval have different durations.

22. The apparatus of claim 21, wherein the preconfigured first and/or second intervals are selected to cause the clock pulse to occur when a symbol is transmitted on the communication interface, thereby permitting the symbol to be reliably sampled.

23. The apparatus of claim 21, wherein the preconfigured first and/or second intervals are configured based on a rise time and a fall time associated with the communication interface, and the rise time corresponds to a rise time associated with an open-drain transistor.

24. The apparatus of claim 23, wherein the preconfigured second interval is selected to match a first delay that is associated with the rise time.

25. The apparatus of claim 24, wherein the preconfigured first interval is selected to match a second delay that is associated with the fall time.

26. The apparatus of claim 21, wherein the processing system is configured to aggregate the first clock pulse with at least one additional clock pulse generated in response to the first transition.

27. The apparatus of claim 21, wherein the processing system is configured to calibrate the preconfigured first and/or second intervals.

28. The apparatus of claim 21, wherein the processing system is configured to:

provide a rising calibration transition on the communication interface;

measure a first delay associated with a first calibration clock pulse generated from the rising calibration transition;

provide a falling calibration transition on the communication interface;

measure a second delay associated with a second calibration clock pulse generated from the falling calibration transition; and

modify at least one preconfigured interval by an amount calculated to minimize a difference between the first delay and the second delay.

29. The apparatus of claim 28, wherein the processing system is configured to modify the at least one preconfigured interval by:

adjusting a programmed delay of the first delay circuit based on a measured delay associated with the first calibration clock pulse; and

adjusting a programmed delay of the second delay circuit based on a measured delay associated with the second calibration clock pulse.

30. The apparatus of claim 28, wherein the processing system is configured to modify the at least one preconfigured interval using a timer that reflects a desired delay associated with the first calibration clock pulse and the second calibration clock pulse.

31. A non-transitory processor-readable storage medium having one or more instructions stored thereon, wherein when executed by at least one processing circuit, the one or more instructions cause the at least one processing circuit to:

receive one or more signals from a multi-wire communication interface, wherein a sequence of symbols is encoded in the one or more signals;

determine a first transition in the one or more signals, wherein the first transition comprises a rising edge;

generate a first clock pulse on a clock signal responsive to the first transition after a preconfigured first interval provided by delaying the first clock pulse using a first delay circuit; and

determine a second transition in the one or more signals, wherein the second transition comprises a rising edge;

generate a second clock pulse on the clock signal responsive to the second transition after a preconfigured second interval provided by delaying the second clock pulse using a second delay circuit,

wherein the preconfigured first interval and the preconfigured second interval have different durations.