Package including an underfill material in a portion of an area between the package and a substrate or another package

• US 9,374,902 B2
• Filed: 05/24/2013
• Issued: 06/21/2016
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yim, Myung Jin, Quevedo, Nanette, Strode, Richard
• Primary Examiner(s): Willis, Tremesha S
• Application Number:
  US13/902,244
• Publication Number:
  US 20130258578A1
• Time in Patent Office: 1,124 Days
• Field of Search: 361/760, 361/761, 361/762, 361/764, 361/767, 361/768, 361/784, 257/528, 257/678, 257/783, 257/789, 174/260
• US Class Current: 1/1
• CPC Class Codes: G06F 1/16 Constructional details or arrangements
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 3/341 : Surface mounted components
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49179 : by metal fusion bonding

Abstract

Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first package, and a second package coupled to the substrate or the first package, wherein the second package includes at least one die and an underfill material disposed in a portion, but not an entirety, of an area between the package and the substrate or the first package. Other embodiments may be described and claimed.

Claims

1. An apparatus, comprising:

a first substrate having a first surface that defines a first plane;

a second substrate having a second surface facing the first surface, wherein the second surface defines a second plane;

an underfill material coupling the second substrate to the first substrate, wherein the underfill material contacts the first surface and the second surface, wherein all of the underfill material is located between the first and second planes and substantially none of the underfill material is located outside of a gap between the first and second substrates, and wherein the underfill material extends along an entire periphery of the second substrate to define a closed chamber between the first and second surface; and

a plurality of solder joints located in the gap, wherein each of the solder joints electrically couples the second substrate to the first substrate, wherein the plurality of solder joints includes a pair of first solder joints each physically contacted by the underfill material such that the underfill material occupies an entire space between the first solder joints and at least a second solder joint is located in the closed chamber and has substantially no physical contact with the underfill material.

2. The apparatus of claim 1, wherein most of the solder joints have substantially no contact with the underfill material.

3. The apparatus of claim 1, wherein the at least the second solder joint includes a plurality of solder joints spaced apart from the underfill material.

4. The apparatus of claim 1, wherein the closed chamber is an unfilled region between the first substrate and the second substrate, wherein the at least the second solder joint is positioned at the unfilled region.

5. The apparatus of claim 1, wherein the underfill material is spaced apart from an array of the solder joints.

6. The apparatus of claim 1, further comprising a package including the second substrate and a die coupled to the second substrate, wherein the plurality of solder joints electrically couple the package to the first substrate.

7. The apparatus of claim 1, wherein the solder joints are connected to respective pads of the first substrate and respective pads of the second substrate.

8. The apparatus of claim 1, further comprising a package coupled to the second substrate by additional solder joints.

9. The apparatus of claim 1, wherein substantially no underfill material is disposed between a center of the second surface and the first substrate.

10. The apparatus of claim 1, wherein the plurality of solder joints are located at a region between the first substrate and the second substrate, wherein the underfill material is positioned at a first portion of the region, wherein a second portion of the region is substantially free of the underfill material, and wherein the at least the second solder joint is positioned at the second portion.

11. The apparatus of claim 1, further comprising a package including a die and at least one of the first substrate or the second substrate.

12. The apparatus of claim 1, wherein the first substrate includes a host logic device bus, and further comprising a flash memory comprising the second substrate.

29. The apparatus of claim 1, wherein the underfill material forms a generally rectangular ring that is spaced apart from and surrounding the at least the second solder joint.

13. An apparatus, comprising:

a first package;

a second package;

an underfill material coupling a second surface of the second package to a first surface of the first package, wherein substantially all of the underfill material is located between a first plane defined by the first surface of the first package and a second plane defined by the second surface of the second package and substantially none of the underfill material is located outside of a gap defined by the first and second packages; and

a plurality of joints electrically coupling the first package to the second package, wherein the underfill material encapsulates each of the joints in a first group such that the underfill material fills an entire space between at least two of the joints in the first group, and wherein at least one of the joints in a second group is located in a closed chamber defined by the underfill material, the first package, and the second package and has substantially no physical contact with the underfill material.

14. The apparatus of claim 13, wherein the underfill material is positioned at a periphery of at least one of the first package and the second package.

15. The apparatus of claim 13, wherein at least one of the joints in the second group electrically couples a pad of the first package to a pad of the second package, and wherein the underfill material has substantially no contact with the pad of the first package and substantially no contact with the pad of the second package.

16. The apparatus of claim 13, further comprising a memory including the first package or the second package.

26. The apparatus of claim 13, wherein the first package has a first die, wherein the second package has a second die and a substrate having the second surface, wherein the second die is located directly between the second surface of the substrate and the first surface of the first package, wherein the apparatus further includes an encapsulant material located in an unfilled region surrounded by the underfill material, and wherein the encapsulant material is disposed over the second die and spaced apart from the first package.

27. The apparatus of claim 13, wherein at least two of the joints are contacted by the underfill material, and wherein the underfill material fills an entire space between the joints contacted by the underfill material.

28. The apparatus of claim 13, wherein the underfill material forms a generally rectangular ring.

17. A method comprising:

depositing an underfill material on an electronic device such that the underfill material contacts first solder bumps and defines uncovered regions of the first solder bumps and the underfill material is spaced apart from second solder bumps;

after depositing the underfill material on the electronic device, moving the uncovered regions of the first solder bumps into contact with a substrate or a package; and

coupling the electronic device to the substrate or the package using the underfill material such that the first and second solder bumps and the underfill material are disposed between the electronic device and the substrate or the package, wherein the underfill material physically contacts the first solder bumps and has substantially no contact with the second solder bumps that electrically couple the electronic device to the substrate or the package, wherein the underfill material contacts a surface of the substrate or the package and a surface of the electronic device and substantially no underfill material is located outside of a space directly between the surface of the substrate or the package and the surface of the electronic device, and wherein the underfill material fills an entire space between adjacent first solder bumps physically contacting and individually embedded in the underfill material.

18. The method of claim 17, wherein coupling the electronic device to the substrate or the package includes:

heating the underfill material to cure the underfill material.

19. The method of claim 18, wherein depositing the underfill material comprises depositing the underfill material on at least one corner of a surface of the electronic device to leave an area between a center of the surface and the substrate or the package substantially free of the underfill material.

20. The method of claim 17, wherein coupling the electronic device to the substrate or the package comprises curing the underfill material while heating the first and second solder bumps to form a corresponding plurality of solder joints.

21. The method of claim 17, wherein the electronic device includes a memory, a package including a die, and/or a host logic device.

22. An apparatus, comprising:

a first substrate;

a second substrate;

a plurality of first solder joints, each of the first solder joints electrically coupling the second substrate to the first substrate;

a plurality of second solder joints, each of the second solder joints electrically coupling the second substrate to the first substrate; and

an underfill material located only directly between the first and second substrates, wherein the underfill material is disposed throughout an entire space between the first solder joints and physically contacts each of the first solder joints, and wherein the underfill material extends about an entire periphery of the first substrate to from a closed chamber and has no contact with the second solder joints in the chamber.

23. A method, comprising:

depositing an underfill material on a first portion of a package having a die such that the underfill material contacts a plurality of first solder bumps and defines uncovered regions of the first solder bumps and such that at least one second solder bump has no contact with the underfill material;

after depositing the underfill material on the first portion of the package, positioning the package carrying the underfill material relative to a substrate or another package such that the uncovered regions of the first solder bumps are moved into contact with the substrate or another package and such that the underfill material and the first and second solder bumps are disposed between the package and the substrate or another package; and

heating the underfill material to couple the package to the substrate or another package, wherein the underfill material occupies an entire space between the first solder bumps such that the underfill material physically contacts and surrounds the first solder bumps.

24. The method of claim 23, wherein depositing the underfill material on the first portion includes depositing the underfill material about an entire periphery of the package with the die.

25. The method of claim 23, wherein positioning the package includes placing the package carrying the underfill material on the substrate or another package after depositing the underfill material on the first portion of the package.