System for reducing peak power during scan shift at the global level for scan based tests

• US 9,377,510 B2
• Filed: 12/28/2012
• Issued: 06/28/2016
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Sonawane, Milind, Puvvada, Satya, Sanghani, Amit
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US13/730,628
• Publication Number:
  US 20140189455A1
• Time in Patent Office: 1,278 Days
• Field of Search: 714/724, 714/726, 714/731, 714733-734, 714/738, 714/742, 714/811, 714/814, 714/815, 714/34, 714/55, 713/400, 713/401, 713/500, 713/501
• US Class Current: 1/1
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318575 Power distribution; Power saving

Abstract

A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.

Claims

1. A method for testing an integrated circuit, said method comprising:

multiplexing a test clock with a functional clock on said integrated circuit at a root of a clock tree to produce a second clock signal;

dividing the second clock signal into multiple branches, wherein each branch is operable to be delayed by a plurality of delay elements, and wherein each branch is delayed by a different number of delay elements of the plurality of delay elements to produce a plurality of lines with variable delay;

routing each line of said plurality of lines with variable delay to a respective plurality of cores and a cache on said integrated circuit, wherein each of the plurality of cores and the cache is operable to be subdivided into a plurality of partitions; and

staggering a third clock signal received by each of the plurality of cores and the cache during a scan shift cycle, wherein the third clock signal is derived from the second clock signal and routed using a respective line of said plurality of lines.

2. The method of claim 1 wherein each of the plurality of cores and the cache receives an active edge of the third clock signal at a separate time.

3. The method of claim 1 further comprising programming a value of the plurality of delay elements.

4. The method of claim 1 wherein said integrated circuit is selected from the group comprising:

a graphics processor and a central processor.

5. The method of claim 1 wherein the clock signal is staggered between each of the plurality of cores and the cache by a constant value.

6. The method of claim 1 further comprising staggering scan test clock pulses transmitted to the plurality of partitions, so that each partition in the plurality of partitions shifts scan data in or out of the partition at a different time from its neighboring partitions.

7. A method for testing an integrated circuit, said method comprising:

multiplexing a test clock with a functional clock on said integrated circuit at a root of a clock tree to produce a second clock signal;

dividing the second clock signal into multiple branches, wherein each branch is operable to be delayed by a plurality of delay elements, and wherein each branch is delayed by a different number of delay elements of the plurality of delay elements;

routing each branch to a respective plurality of cores and a cache on said integrated circuit, wherein each of the plurality of cores and the cache is operable to be subdivided into a plurality of partitions; and

staggering a third clock signal received by each of the plurality of cores and the cache during a scan shift cycle, wherein each of the plurality of cores and the cache receives an active edge of the second clock signal at a separate time, wherein the third clock signal is derived from the second clock signal and routed using a respective branch of the multiple branches.

8. The method of claim 7 further comprising programming a value of the plurality of delay elements.

9. The method of claim 7 wherein said integrated circuit is selected from the group comprising:

a graphics processor and a central processor.

10. The method of claim 7 wherein the third clock signal is staggered between each of the plurality of cores and the cache by a constant value.

11. The method of claim 7 further comprising staggering scan test clock pulses transmitted to the plurality of partitions, so that each partition in the plurality of partitions shifts scan data in or out of the partition at a different time from its neighboring partitions.

12. A system for testing an integrated circuit, said system comprising:

a computer system comprising a tester processor, wherein said tester processor is communicatively coupled to a integrated circuit, wherein said integrated circuit comprises;

a plurality of I/O ports, wherein at least one I/O port is associated with a test clock signal driven by said tester processor;

a multiplexer operable to multiplex the test clock signal with a functional clock signal at a root of a clock tree;

a plurality of cores and a cache, wherein each of the plurality of cores and the cache is operable to be subdivided into a plurality of partitions, wherein each partition employs a SerDes scan architecture; and

a clock trimmer module comprising a plurality of delay elements operable to add delay to a clock path signal, wherein said clock path signal is an output of said multiplexer and wherein the plurality of delay elements are operable to stagger a respective test clock received by each of the plurality of cores and the cache via the clock path signal.

13. The system of claim 12 wherein each of the plurality of cores and the cache receives an active edge of the respective test clock at a separate time.

14. The system of claim 12 wherein said integrated circuit further comprises JTAG bits operable to program the plurality of delay elements.

15. The system of claim 12 wherein said integrated circuit is selected from the group comprising:

a graphics processor and a central processor.

16. The system of claim 12 wherein the clock path signal is staggered between each of the plurality of cores and the cache by a constant value.