Restricting clock signal delivery based on activity in a processor

• US 9,377,836 B2
• Filed: 07/26/2013
• Issued: 06/28/2016
• Est. Priority Date: 07/26/2013
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gendler, Alexander, Leifman, George
• Primary Examiner(s): Tran, Vincent
• Application Number:
  US13/951,646
• Publication Number:
  US 20150033051A1
• Time in Patent Office: 1,068 Days
• Field of Search: 713/322
• US Class Current: 1/1
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/34 Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
• CPC Class Codes: G06F 11/3433 for load management allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In an embodiment, a processor has a core to execute instructions which includes a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the units to a first frequency less than a frequency of the first clock signal. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a core to execute instructions, the core including a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the plurality of units to a first frequency less than a frequency of the first clock signal, wherein the core activity monitor logic is to send a second restriction command, responsive to a miss in a second cache memory coupled to the core, the second restriction command to cause the clock generation logic to reduce the first clock signal delivery to a second frequency less than the first frequency.

2. The processor of claim 1, wherein the core activity monitor logic is to send a third restriction command, responsive to a stall in a first one of the plurality of units, the third restriction command to cause the clock generation logic to reduce the first clock signal delivery to a third frequency less than the second frequency.

3. The processor of claim 1, wherein the first cache memory comprises a private cache memory and the second cache memory comprises a shared cache memory.

4. The processor of claim 1, wherein the core activity monitor logic is to remove the first restriction command responsive to receipt in the core of data associated with the first cache memory miss, to cause the clock generation logic to distribute the first clock signal without restriction.

5. The processor of claim 1, wherein the first restriction command is associated with a first toggle pattern to cause the clock generation logic to distribute the first clock signal with M toggles in N clock cycles, where N is greater than M.

6. The processor of claim 1, wherein the clock generation logic is to perform the reduced delivery independently of a power control unit (PCU) coupled to the core.

7. The processor of claim 1, wherein the clock generation logic is to prevent a first number of cycles of the first clock signal from being distributed to the plurality of units for each cycle of the first clock signal distributed to the plurality of units.

8. The processor of claim 1, wherein the plurality of units includes a first subset of units to receive the first clock signal with the reduced delivery and a second subset of units to receive the first clock signal without restriction.

9. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

receiving, in a monitor logic of a core of a processor, at least one of first information regarding a first miss in a first cache memory and second information regarding a second miss in a second cache memory, the first cache memory included in the core and the second cache memory coupled to the core;

sending a clock restriction command, from the monitor logic to a clock generation circuit of the core, with a first restriction level responsive to the first information and with a second restriction level responsive to the second information; and

controlling the clock generation circuit according to the first restriction level or the second restriction level to drive a restricted clock signal to at least one functional unit of the core, wherein the restricted clock signal includes a reduced number of cycles of a clock signal of the core based on the first restriction level or the second restriction level.

10. The non-transitory machine-readable medium of claim 9, wherein the method further comprises operating the core with the clock signal without restriction and thereafter operating the core with the restricted clock signal, without stopping the core.

11. The non-transitory machine-readable medium of claim 9, wherein the method further comprises sending the clock restriction command to the clock generation circuit with a third restriction level responsive to a stall occurring in the core.

12. The non-transitory machine-readable medium of claim 9, wherein the method further comprises driving the restricted clock signal to the at least one functional unit with a first number of active toggles during a time period in a first power mode and driving the restricted clock signal to the at least one functional unit with a second number of active toggles during the time period in a second power mode, the first power mode a power saving mode and the second number of active toggles greater than the first number of active toggles.

13. A system comprising:

a multicore processor including;

a plurality of cores, each core including;

at least one cache memory;

a clock generator to receive and distribute a first clock signal to a plurality of units of the core;

a restriction logic to receive a clock restriction command and to cause reduced delivery of the first clock signal to at least one of the plurality of units; and

an activity monitor to communicate the clock restriction command to the restriction logic responsive to an event occurring in the core, wherein the activity monitor is to communicate the clock restriction command to the restriction logic with a first toggle pattern responsive to a miss in the at least one cache memory, and communicate the clock restriction command to the restriction logic with a second toggle pattern responsive to a miss in a second cache memory coupled to the core; and

a clock logic to provide the first clock signal to at least one of the plurality of cores; and

a dynamic random access memory (DRAM) coupled to the multicore processor.

14. The system of claim 13, wherein the activity monitor is to communicate the clock restriction command to the restriction logic with a third toggle pattern responsive to a stall in a first one of the plurality of units.

15. The system of claim 14, wherein the first toggle pattern is to cause the reduced delivery of the first clock signal at a first frequency less than a frequency of the first clock signal, the second toggle pattern is to cause the reduced delivery of the first clock signal at a second frequency less than the first frequency, and the third toggle pattern is to cause the reduced delivery of the first clock signal at a third frequency less than the second frequency.

16. The system of claim 13, wherein the plurality of units includes a first subset of units to receive the first clock signal with the reduced delivery and a second subset of units to receive the first clock signal without restriction.