×

Restricting clock signal delivery based on activity in a processor

  • US 9,377,836 B2
  • Filed: 07/26/2013
  • Issued: 06/28/2016
  • Est. Priority Date: 07/26/2013
  • Status: Expired due to Fees
First Claim
Patent Images

1. A processor comprising:

  • a core to execute instructions, the core including a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the plurality of units to a first frequency less than a frequency of the first clock signal, wherein the core activity monitor logic is to send a second restriction command, responsive to a miss in a second cache memory coupled to the core, the second restriction command to cause the clock generation logic to reduce the first clock signal delivery to a second frequency less than the first frequency.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×