Multilayer quality of service (QOS) for network functions virtualization platforms

• US 9,378,043 B1
• Filed: 05/28/2015
• Issued: 06/28/2016
• Est. Priority Date: 05/28/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Zhang, Jiefan, Rabi, Abdel Hafiz, Kugel, Alexander, Chen, Allen, Lewis, Mark Jonathan
• Primary Examiner(s): Nguyen, Phillip H
• Application Number:
  US14/724,089
• Time in Patent Office: 397 Days
• Field of Search: 718/1, 718/102, 718/103
• US Class Current: 1/1
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: H04L 49/70 Virtual switches

Abstract

A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The traffic at the NFV platform may be controlled by a distributed Quality of Service (QoS) manager. The distributed QoS manager may include multiple QoS modules each of which serves to perform priority queuing independently for its associated component or interface. For example, the NFV platform may include a first QoS module for arbitrating among multiple virtual machines, a second QoS module for performing priority queuing for data packets received at an external network port, a third QoS module for arbitrating among memory accesses at a coprocessor external memory interface, fourth QoS module for arbitrating accesses among multiple hardware acceleration slices, etc.

Claims

1. An integrated circuit, comprising:

a first circuit that receives service requests from a plurality of virtual machines, wherein the service requests are scheduled using a virtual machine manager (VMM) Quality of Service (QoS) module; and

a second circuit that receives data packets from an external data port, wherein traffic at the external data port is managed using a network ingress-egress Quality of Service (QoS) module that is different than the virtual machine manager QoS module.

2. The integrated circuit defined in claim 1, wherein the virtual machine manager QoS module operates independently from the network ingress-egress QoS module.

3. The integrated circuit defined in claim 1, wherein the first circuit comprises a direct memory access (DMA) engine.

4. The integrated circuit defined in claim 3, wherein the DMA engine comprises:

a plurality of input queues that is managed using the virtual machine manager QoS module; and

a plurality of output queues that is managed using a data switch Quality of Service (QoS) module which operates independently from the VMM QoS module.

5. The integrated circuit defined in claim 1, further comprising:

data switching circuitry that is coupled to the first circuit and the second circuit and that communicates directly with a plurality of virtual function hardware accelerators within the integrated circuit, wherein communications with the plurality of virtual function hardware accelerators at the data switching circuitry is managed using a hardware accelerator input-output QoS module that operates independently from the virtual machine manager QoS module and the network ingress-egress QoS module.

6. The integrated circuit defined in claim 1, further comprising:

a memory controller for communicating with an external memory device, wherein memory access requests at the memory controller is prioritized using an external memory Quality of Service (QoS) module that operates independently from the virtual machine manager QoS module and the network ingress-egress QoS module.

7. The integrated circuit defined in claim 1, wherein the plurality of virtual machines is running on an external host processor that is coupled to the integrated circuit and that runs a hypervisor.

8. The integrated circuit defined in claim 1, further comprising:

programmable logic elements that can be reconfigured to perform different custom functions.

9. A method of managing traffic for a network functions virtualization (NFV) system, comprising:

using a first Quality of Service (QoS) module to prioritize service requests from at least one virtual machine running on a host processor in the NFV system; and

using a second Quality of Service (QoS) module to perform priority scheduling independently from the first QoS module, wherein the second QoS is included within a coprocessor that is attached to the host processor in the NFV system.

10. The method defined in claim 9, wherein using the first QoS module comprises using the first QoS module to prioritize service requests from different classes of services from the at least one virtual machine running on the host processor.

11. The method defined in claim 9, wherein using the first QoS module comprises using a virtual machine manager (VMM) QoS module to priority service requests from a plurality of virtual machines running on the host processor.

12. The method defined in claim 10, wherein using the second QoS module comprises:

using a data switch Quality of Service (QoS) module to prioritize data that is being fed back to the plurality of virtual machines.

13. The method defined in claim 10, wherein using the second QoS module comprises:

using a network ingress Quality of Service (QoS) module to manage incoming traffic at an external data port of the coprocessor; and

using a network egress Quality of Service (QoS) module to manage outgoing traffic at the external data port of the coprocessor.

14. The method defined in claim 10, wherein using the second QoS module comprises:

using a hardware accelerator input Quality of Service (QoS) module to manage incoming traffic to a plurality of hardware accelerators in the coprocessor; and

using a hardware accelerator output Quality of Service (QoS) module to manage outgoing traffic produced from the plurality of hardware accelerators in the coprocessor.

15. The method defined in claim 10, wherein using the second QoS module comprises:

using an external memory Quality of Service (QoS) module to prioritize memory accesses to an off-chip memory device that is directly attached to the coprocessor.

16. A Network Functions Virtualization (NFV) platform, comprising:

a host processor having a hypervisor that creates and runs virtual machines; and

a coprocessor having accelerators for accelerating the performance of the virtual machines, wherein the host processor and the coprocessor includes a multilayer Quality of Service (QoS) manager having a plurality of independently operating QoS modules distributed throughout the NFV platform.

17. The NFV platform defined in claim 16, wherein the plurality of QoS modules includes at least seven independently operated QoS modules.

18. The NFV platform defined in claim 16, wherein the plurality of QoS modules includes a Class of Service (CoS) QoS module that prioritizes service requests from at least one of the virtual machines running on the host.

19. The NFV platform defined in claim 16, wherein the plurality of QoS modules includes a virtual machine manager (VMM) QoS module to priority service requests from the virtual machines running on the host processor.

20. The NFV platform defined in claim 16, wherein the plurality of QoS modules includes a data switch QoS module to prioritize data that is being fed back from the coprocessor to the virtual machines on the host processor.

21. The NFV platform defined in claim 16, wherein the plurality of QoS modules includes a network ingress-egress QoS module for managing traffic at an external data port of the coprocessor.

22. The NFV platform defined in claim 16, wherein the plurality of QoS modules includes a hardware accelerator QoS module for managing traffic with a plurality of hardware accelerators in the coprocessor.

23. The NFV platform defined in claim 16, wherein the plurality of QoS modules includes an external memory QoS module for prioritizing memory accesses to an off-chip memory device that is directly attached to the coprocessor.