Interruption of chip component managing tasks

• US 9,378,048 B2
• Filed: 06/11/2014
• Issued: 06/28/2016
• Est. Priority Date: 05/14/2013
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brock, Bishop, Gloekler, Tilman, Koenig, Andreas, Lichtenau, Cedric, Lobo, Preetham M.
• Primary Examiner(s): Lee, Adam
• Application Number:
  US14/302,120
• Publication Number:
  US 20140344824A1
• Time in Patent Office: 748 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 9/46 Multiprogramming arrangements
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups

Abstract

Embodiments include receiving, at a microcontroller of a chip, a request to execute a first task having a first priority. Embodiments further include determining that a second task having a second priority is currently executing. Embodiments further include determining that the first priority is higher than the second priority. Embodiments further include determining whether a value in a register indicates that the second task can be interrupted. If it is determined that the second task can be interrupted, embodiments further include triggering execution of the second task. If it is determined that the second task cannot be interrupted, embodiments further include waiting for lapse of a time period since receipt of the request to execute the first task, and interrupting the second task upon detecting lapse of the time period, or detecting, prior to the lapse of the time period, that the second task can be interrupted.

Claims

1. A method comprising:

determining a current state value associated with a currently executing task at a microcontroller of a chip;

storing the current state value in a register;

determining whether a first priority of a requested task is higher than a second priority of the currently executing task;

in response to determining that the first priority is higher than the second priority, evaluating the current state value stored in the register and determining a time interval since receiving a request to execute the requested task;

in response to evaluating the current state value stored in the register as indicating interruptible or determining the time interval exceeds a threshold, interrupting the currently executing task and triggering execution of the requested task on the chip; and

in response to evaluating the current state value stored in the register as indicating uninterruptible and the time interval does not exceed the threshold, executing the requested task in response to detection of one member selected from the group consisting of;

detection of graceful termination of the currently executing task and detection of a change to the current state value.

2. The method of claim 1, further comprising:

monitoring the current state value.

3. The method of claim 1, wherein the request to execute the requested task includes an attribute value indicating the first priority.

4. The method of claim 1, wherein the first priority and the second priority are determined based, at least in part, on a first type of the requested task and a second type of the currently executing task.

5. The method of claim 1, wherein the requested task is one of a first group of tasks and wherein the currently executing task is one of a second group of tasks, wherein tasks of the first group of tasks are responsible for one or more of booting a processor core of the chip, initializing a processor core of the chip, shutting down a processor core of the chip, protecting a processor core of the chip against overheating, and managing an energy supply of a processor core of the chip, and wherein tasks of the second group of tasks are responsible for monitoring a processor core of the chip, clocking a processor core of the chip, creating usage statistics for a processor core of the chip, and identifying errors and invalid states of a processor core of the chip.

6. The method of claim 1, wherein the request to execute the requested task indicates the threshold.