Autonomous initialization of non-volatile random access memory in a computer system

• US 9,378,133 B2
• Filed: 09/30/2011
• Issued: 06/28/2016
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nachimuthu, Murugasamy K., Kumar, Mohan, Ziakas, Dimitrios
• Primary Examiner(s): Farrokh, Hashem
• Application Number:
  US13/997,945
• Publication Number:
  US 20130304980A1
• Time in Patent Office: 1,733 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM.

Claims

1. An apparatus comprising:

a non-volatile random access memory (NVRAM) controller having a first interface to communicatively couple to a processor, the NVRAM controller having a second interface to communicatively couple to an NVRAM, the NVRAM being byte-rewritable and byte-erasable by the processor so that the NVRAM behaves as a system memory, the NVRAM to store thereon a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of a computer system without interacting with the processor and firmware outside of the NVRAM, to thereby allow access to the NVRAM by the computer system, the memory interface table to contain a pointer to BIOS program code that is stored in the NVRAM, the apparatus further comprising a plurality of NVRAM controllers to manage the NVRAM, each of the NVRAM controllers to manage a respective portion of the NVRAM and wherein one of the NVRAM controllers is a boot agent to autonomously initialize the NVRAM, wherein the boot agent is to respond to a query from the computer system to identify itself as the boot agent.

2. The apparatus of claim 1, wherein, after autonomous initialization of the NVRAM, the NVRAM controller is to provide the processor with the pointer in the memory interface table to allow the processor to access the BIOS program code and to thereby boot up the computer system.

3. The apparatus of claim 1, further comprising:

a micro-controller coupled to the processor;

a main power rail to supply power to the processor; and

a standby power rail to support standby power to the micro-controller,

wherein the micro-controller is to use information in the memory interface table to access microcontroller firmware in the NVRAM when the main power rail does not supply power to the computer system.

4. The apparatus of claim 3, wherein the micro-controller is a Management Engine (ME).

5. The apparatus of claim 1, wherein the NVRAM comprises phase change memory (PCM).

6. The apparatus of claim 1, wherein the NVRAM contains a plurality of regions and the memory interface table is to contain a plurality of location pointers, with each of the location pointers pointing to one of the regions.

7. The apparatus of claim 6, wherein the plurality of regions comprises one or more of the following:

Serial Presence Detect (SPD) data, device-specific initialization sequences, system configuration data, error maps and redundant regions.

8. The apparatus of claim 1, wherein the NVRAM has stored thereon error maps, wherein the NVRAM controller is to identify corrupted areas of the NVRAM using the error maps and to reconfigure the NVRAM using redundant regions in the NVRAM to exclude the corrupted areas from use.

9. The apparatus of claim 1,

wherein the NVRAM has stored thereon system configuration data, which describes how the plurality of NVRAM controllers and the NVRAM are connected to the computer system.

10. A method comprising:

receiving a power-on signal in a computer system, the computer system comprising a processor and a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor;

reading, by an NVRAM controller coupled to the NVRAM, a memory interface table in the NVRAM;

autonomously initializing, by the NVRAM controller, the NVRAM using information in the memory interface table upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM, the information being a pointer to BIOS program code within NVRAM;

providing the information to the processor to allow the processor to access the BIOS program code within the NVRAM to boot up the computer system;

accessing the NVRAM by the processor where the processor views the NVRAM as a system memory;

wherein the NVRAM comprises a plurality of NVRAM controllers including the NVRAM controller, with each controller managing a portion of the NVRAM, the method further comprising;

receiving, by the plurality of NVRAM controllers, a query from the computer system for a boot agent; and

,

in response to the query, one of the plurality of the NVRAM controllers identifying itself as the boot agent.

11. The method of claim 10, further comprising:

after autonomous initialization of the NVRAM, providing by the NVRAM controller to the processor the pointer in the memory interface table to allow the processor to access the BIOS and to thereby boot up the computer system.

12. The method of claim 10, wherein the computer system comprises:

a micro-controller coupled to the processor, a main power rail to supply power to the processor, and a standby power rail to support standby power to the micro-controller, the method further comprising;

providing the information to the micro-controller to allow the micro-controller to;

access micro-controller firmware stored in the NVRAM when the main power rail does not supply power to the computer system.

13. The method of claim 10, wherein the NVRAM comprises phase change memory (PCM).

14. The method of claim 10, wherein the NVRAM contains a plurality of regions and wherein reading the memory interface table in the NVRAM further comprises:

locating one of a plurality of location pointers in the memory interface table; and

locating a corresponding one of the regions by following the one of the location pointers,

wherein the plurality of regions comprises one or more of the following;

Serial Presence Detect (SPD) data, device-specific initialization sequences, system configuration data, error maps and redundant regions.

15. The method of claim 10, wherein the NVRAM has stored thereon error maps and redundant regions, the method further comprising:

identifying corrupted areas of the NVRAM using the error maps; and

reconfiguring the NVRAM using the redundant regions to exclude the corrupted areas from use.

16. A system comprising:

a processor in a computer system;

a main power rail coupled to the processor;

a standby power rail;

a non-volatile random access memory (NVRAM) controller coupled to the processor; and

an NVRAM coupled to the controller and coupled to both the main power rail and the standby power rail, the NVRAM being byte-rewritable and byte-erasable by the processor so that the NVRAM behaves as a system memory, the NVRAM having stored thereon a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM when either the main power rail or the standby power rail turns on power without interacting with the processor and firmware outside of the NVRAM, to thereby allow access to the NVRAM by the computer system, the memory interface table to contain a pointer to BIOS program code that is stored in the NVRAM, the system further comprising a plurality of NVRAM controllers to manage the NVRAM, each of the NVRAM controllers to manage a respective portion of the NVRAM and wherein one of the NVRAM controllers is a boot agent to autonomously initialize the NVRAM, wherein the boot agent is to respond to a query from the computer system to identify itself as the boot agent.

17. The system of claim 16, wherein, after autonomous initialization of the NVRAM, the NVRAM controller is to provide the processor with the pointer in the memory interface table to allow the processor to access the BIOS program code and to thereby boot up the computer system.

18. The system of claim 16, further comprising:

a micro-controller coupled to the processor and the standby power rail,

wherein the micro-controller uses information in the memory interface table to access microcontroller firmware in the NVRAM when the main power rail does not supply power to the computer system.

19. The system of claim 16, wherein the NVRAM comprises phase change memory (PCM).

20. The system of claim 16, wherein the NVRAM contains a plurality of regions and the memory interface table is to contain a plurality of location pointers, with each of the location pointers pointing to one of the regions, wherein the plurality of regions comprises one or more of the following:

Serial Presence Detect (SPD) data, device-specific initialization sequences, system configuration data, error maps and redundant regions.

21. The system of claim 16, wherein the NVRAM has stored thereon error maps, wherein the NVRAM controller is to identify corrupted areas of the NVRAM using the error maps and to reconfigure the NVRAM using redundant regions in the NVRAM to exclude the corrupted areas from use.