Gate driving circuit and method, and liquid crystal display
First Claim
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1. A gate driving circuit comprising shift registers at a plurality of stages, wherein the shift register at each stage including a pull-up driving unit, a pull-up unit, a reset unit and a pull-down unit, said shift register further including:
- a supplementary unit;
wherein,said pull-up unit is connected to an output terminal of the shift register at a present stage and is used for making a clock signal at a first clock terminal an output signal at the output terminal when being turned on;
said supplementary unit is connected to the output terminal of the shift register at the present stage, and is used for making a clock signal at a second clock terminal the output signal at the output terminal when being turned on;
said pull-down unit is connected to the output terminal of the shift register at the present stage, and is used for making a low level at a low voltage signal terminal the output signal at the output terminal when being turned on,wherein a first voltage corresponding to a high level of the clock signal at the first clock terminal is higher than a second voltage corresponding to a high level of the clock signal at the second clock terminal, such that the output signal at the output terminal of the shift register at the present stage lumps from the first voltage to the second voltage and then to the low level at the low voltage signal terminal.
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Abstract
The present disclosure provides a gate driving circuit, a gate driving method and a liquid crystal display. Said gate driving circuit includes shift registers at a plurality of stages, wherein the shift register at each stage includes a pull-up driving unit, a pull-up unit, a reset unit, a pull-down unit and a supplementary unit; said pull-up unit is used for making a clock signal at a first clock terminal an output signal of the shift register at the present stage when being turned on; said supplementary unit, connected to said pull-up unit, is used for making a clock signal at a second clock terminal the output signal of the shift register at the present stage when being turned on. With the supplementary unit, the present disclosure can reduce voltage jump of a pixel, achieve the MLG function and enhance the picture quality of the LCD.
15 Citations
20 Claims
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1. A gate driving circuit comprising shift registers at a plurality of stages, wherein the shift register at each stage including a pull-up driving unit, a pull-up unit, a reset unit and a pull-down unit, said shift register further including:
- a supplementary unit;
wherein,said pull-up unit is connected to an output terminal of the shift register at a present stage and is used for making a clock signal at a first clock terminal an output signal at the output terminal when being turned on; said supplementary unit is connected to the output terminal of the shift register at the present stage, and is used for making a clock signal at a second clock terminal the output signal at the output terminal when being turned on; said pull-down unit is connected to the output terminal of the shift register at the present stage, and is used for making a low level at a low voltage signal terminal the output signal at the output terminal when being turned on, wherein a first voltage corresponding to a high level of the clock signal at the first clock terminal is higher than a second voltage corresponding to a high level of the clock signal at the second clock terminal, such that the output signal at the output terminal of the shift register at the present stage lumps from the first voltage to the second voltage and then to the low level at the low voltage signal terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- a supplementary unit;
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9. A liquid crystal display comprising a gate driving circuit comprising shift registers at a plurality of stages, wherein the shift register at each stage including a pull-up driving unit, a pull-up unit, a reset unit and a pull-down unit, said shift register further including:
- a supplementary unit;
wherein,said pull-up unit is connected to an output terminal of the shift register at a present stage and is used for making a clock signal at a first clock terminal an output signal at the output terminal when being turned on; said supplementary unit is connected to the output terminal of the shift register at the present stage, and is used for making a clock signal at a second clock terminal the output signal at the output terminal when being turned on; said pull-down unit is connected to the output terminal of the shift register at the present stage, and is used for making a low level at a low voltage signal terminal the output signal at the output terminal when being turned on, wherein a first voltage corresponding to a high level of the clock signal at the first clock terminal is higher than a second voltage corresponding to a high level of the clock signal at the second clock terminal, such that the output signal at the output terminal of the shift register at the present stage lumps from the first voltage to the second voltage and then to the low level at the low voltage signal terminal. - View Dependent Claims (10, 11, 12, 13, 14)
- a supplementary unit;
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15. A gate driving method for a gate driving circuit comprising shift registers at a plurality of stages, wherein the shift register at each stage including a pull-up driving unit, a pull-up unit, a reset unit and a pull-down unit, said shift register further including:
- a supplementary unit;
wherein,said pull-up unit is connected to an output terminal of the shift register at a present stage and is used for making a clock signal at a first clock terminal an output signal at the output terminal when being turned on; said supplementary unit is connected to the output terminal of the shift register at the present stage, and is used for making a clock signal at a second clock terminal the output signal at the output terminal when being turned on; said pull-down unit is connected to the output terminal of the shift register at the present stage, and is used for making a low level at a low voltage signal terminal the output signal at the output terminal when being turned on, the gate driving method comprising; turning on the pull-up driving unit and beginning to charge the shift register at the present stage when the output signal at the output terminal of the shift register at a previous stage is at a high level; turning on the pull-up unit and making the clock signal at the first clock terminal the output signal of the shift register at the present stage when the clock signal at the first clock terminal is at its high level and the clock signal at the second clock terminal is at a low level; the clock signal at said first clock terminal jumping into the low level, the clock signal at said second clock terminal jumping into its high level, turning on the supplementary unit and making the clock signal at said second clock terminal the output signal of the shift register at the present stage, wherein a first voltage corresponding to the high level of the clock signal at the first clock terminal is higher than a second voltage corresponding to the high level of the clock signal at the second clock terminal, such that the output signal at the output terminal of the shift register at the present stage lumps from the first voltage to the second voltage and then to the low level at the low voltage signal terminal. - View Dependent Claims (16, 17, 18, 19, 20)
- a supplementary unit;
Specification
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Current AssigneeBeijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
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Original AssigneeBeijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
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InventorsChen, Xi, Cui, Wenhai
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Primary Examiner(s)Wang-Hurst, Kathy
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Assistant Examiner(s)Shen, Peijie
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Application NumberUS13/884,713Publication NumberTime in Patent Office1,313 DaysField of SearchUS Class Current1/1CPC Class CodesG09G 2310/0286 Details of a shift register...G09G 2320/0223 Compensation for problems r...G09G 2320/041 Temperature compensationG09G 3/3611 Control of matrices with ro...G09G 3/3677 suitable for active matrice...G11C 19/28 using semiconductor element...
