Systems and methods for last written page handling in a memory device
First Claim
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1. A system for reading data, the system comprising:
- a memory read circuit operable to access a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells;
a controller circuit operable to;
determine that the group of memory cells was a last written group of memory cells; and
based at least in part on determining that the group of memory cells was the last written group of memory cells, cause the memory read circuit to re-access the data set from the group of memory cells using a last written reference value to distinguish the bit values in the group of memory cells.
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Abstract
Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells.
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Citations
20 Claims
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1. A system for reading data, the system comprising:
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a memory read circuit operable to access a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells; a controller circuit operable to; determine that the group of memory cells was a last written group of memory cells; and based at least in part on determining that the group of memory cells was the last written group of memory cells, cause the memory read circuit to re-access the data set from the group of memory cells using a last written reference value to distinguish the bit values in the group of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for recovering data from a memory device, the method comprising:
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providing a flash memory circuit including a superset of memory cells; accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, wherein the group of memory cells is a subset of the superset of memory cells; determine that the group of memory cells was a last written group of memory cells; and based at least in part on determining that the group of memory cells was the last written group of memory cells, re-accessing the data set from the group of memory cells using a last written reference value to distinguish the bit values in the group of memory cells. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A flash memory storage system, the system comprising:
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a flash memory circuit including a superset of flash memory cells; a memory read circuit operable to access a data set from a group of flash memory cells using a standard reference value to distinguish bit values in the group of flash memory cells, wherein the group of flash memory cells is a subset of the superset of flash memory cells; a controller circuit operable to; determine that the group of flash memory cells was a last written group of cells; and based at least in part on determining that the group of flash memory cells was a last written group of cells, causing the memory read circuit to re-access the data set from the group of flash memory cells using a last written reference value to distinguish the bit values in the group of flash memory cells; a hard decision decoder circuit operable to; apply a hard decision decode algorithm to the data set from the group of flash memory cells accessed using the standard reference value to yield a first decode output; and apply the hard decision decode algorithm to the data set from the group of flash memory cells accessed using the last written reference value to yield a second decode output; and wherein the controller circuit determines that the group of flash memory cells was the last written group of flash memory cells based at least in part on the occurrence of one or more errors in the first decode output.
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Specification