Variable resistance memory devices and erase verifying methods thereof

• US 9,378,816 B2
• Filed: 08/30/2013
• Issued: 06/28/2016
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kanamori, Kohji
• Primary Examiner(s): Alrobaie, Khamdan
• Application Number:
  US14/015,869
• Publication Number:
  US 20140063914A1
• Time in Patent Office: 1,033 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Abstract

An erase verifying method includes applying a first voltage to a plurality of word lines connected to a memory cell block, and applying a second voltage less than the first voltage to a plurality of bit lines connected to the memory cell block. The method includes sensing bit line currents flowing through the plurality of bit lines, and comparing the sensed bit line currents with a reference current. The method also includes determining that the memory cell block has been sufficiently erased by a first erase operation if each of the sensed bit line currents is less than the reference current.

Claims

1. An erase verifying method of a variable resistance memory device having a plurality of bit lines connected to a memory cell block, the method, comprising:

applying a first voltage to a plurality of word lines connected to the memory cell block;

applying a second voltage less than the first voltage to the plurality of bit lines connected to the memory cell block;

sensing bit line currents flowing through the plurality of bit lines from the plurality of word lines;

comparing the sensed bit line currents with a reference current; and

determining that the memory cell block has been sufficiently erased by a first erase operation if each of the sensed bit line currents is less than the reference current,

wherein the reference current is based on a product of the number of the plurality of word lines and an erase current, the erase current being a current flowing through a memory cell of the memory cell block.

2. The erase verifying method of claim 1, wherein the second voltage is a ground voltage.

3. The erase verifying method of claim 1, wherein the applying a first voltage includes applying the first voltage to all word lines connected to the memory cell block.

4. The erase verifying method of claim 1, further comprising:

determining that the memory cell block has not been sufficiently erased by the first erase operation if at least one of the sensed bit line currents is greater than the reference current; and

performing a second erase operation on the memory cell block.

5. The erase verifying method of claim 1, wherein the memory cell has a variable resistance value corresponding to an erase resistance, the erase resistance being a lower limit resistance value of the memory cell in an erased state.

6. The erase verifying method of claim 5, wherein the reference current has a value greater than a product of the number of the plurality of word lines and the erase current.

7. The erase verifying method of claim 1, wherein the reference current has a value less than a program current, the program current being a current flowing through a memory cell of the memory block, the memory cell having a variable resistance value corresponding to a program resistance, the program resistance being an upper limit resistance value of the memory cell in a programmed state.

8. The erase verifying method of claim 1, wherein the applying a second voltage includes applying the second voltage to all bit lines connected to the memory cell block.

9. An erase verifying method of a variable resistance memory device having a plurality of bit line groups connected to a memory cell block, each bit line group including more than one bit line, the method comprising:

selecting one of the plurality of bit line groups;

applying a first voltage to a plurality of word lines connected to the memory cell block;

applying a second voltage less than the first voltage to the selected one of the plurality of bit line groups;

applying the first voltage to unselected bit line groups;

sensing bit line currents flowing through bit lines in the selected bit line group from the plurality of word lines;

determining whether the memory cell block is sufficiently erased based on the sensed bit line currents,

providing a reference current which is greater than a product of a number of the plurality of word lines and an erase current and less than a program current, the erase current being a current flowing through a first memory cell of the memory cell group; and

comparing the sensed bit line currents with the reference current during the determining step.

10. The erase verifying method of claim 9, wherein the determining comprises:

selecting a next bit line group if each of the sensed bit line currents is less than the reference current.

11. The erase verifying method of claim 10, wherein the memory cell block is determined to be sufficiently erased if each of the sensed bit line currents of all selected bit line groups is less than the reference current.

12. The erase verifying method of claim 10, wherein the first memory cell has a variable resistance value corresponding to an erase resistance, the erase resistance being a lower limit resistance value of the first memory cell in an erased state, the program current being a current flowing through a second memory cell of the memory cell group, the second memory cell having a variable resistance value corresponding to a program resistance, the program resistance being an upper limit resistance value of the second memory cell in a programmed state.