Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device

• US 9,378,817 B2
• Filed: 03/22/2012
• Issued: 06/28/2016
• Est. Priority Date: 03/25/2011
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Inventors: Kawai, Ken, Shimakawa, Kazuhiko, Katoh, Yoshikazu
• Primary Examiner(s): Luu, Pho M
• Assistant Examiner(s): Bashar, Mohammed A
• Application Number:
  US13/581,925
• Publication Number:
  US 20130188414A1
• Time in Patent Office: 1,559 Days
• Field of Search: 365/148, 365/189.16
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse

Abstract

A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance element, reversibly changing the variable resistance element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse is provided. The variable resistance nonvolatile memory element writing method includes applying a first preliminary voltage pulse and subsequently applying the first voltage pulse to the variable resistance element to change the variable resistance element from the second resistance state to the first resistance state, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.

Claims

1. A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance nonvolatile memory element, reversibly changing the variable resistance nonvolatile memory element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse,

wherein the variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer placed between the first electrode and the second electrode,

the variable resistance layer includes an oxygen-deficient first transition metal oxide layer that is in contact with the first electrode, and a second transition metal oxide layer that is in contact with the second electrode and is lower in oxygen deficiency than the first transition metal oxide layer, and

the variable resistance nonvolatile memory element has characteristics of changing to the first resistance state when, with respect to one of the first electrode and the second electrode, a first voltage pulse having a positive potential and equal to or more than a first threshold voltage is applied to an other one of the first electrode and the second electrode, and changing to the second resistance state when, with respect to the other one of the first electrode and the second electrode, a second voltage pulse having a positive potential and equal to or more than a second threshold voltage is applied to the one of the first electrode and the second electrode,

the variable resistance nonvolatile memory element writing method comprising

during a writing operation, successively applying a first voltage pulse set and a memory cell value measurement a plurality of times, the first voltage pulse set including a first preliminary voltage pulse and the first voltage pulse, wherein in the first voltage pulse set, the first voltage pulse is applied to the variable resistance nonvolatile memory element subsequent to the first preliminary voltage pulse when changing the variable resistance nonvolatile memory element from the second resistance state to the first resistance state, such that a value of the memory cell changes in accordance with each successive application of the first voltage pulse set, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.

2. The variable resistance nonvolatile memory element writing method according to claim 1,

wherein the applying the first voltage pulse set is repeatedly performed the plurality of times to change the variable resistance nonvolatile memory element from the second resistance state to the first resistance state.

3. The variable resistance nonvolatile memory element writing method according to claim 1,

wherein the first resistance state is a high resistance state, and the second resistance state is a low resistance state that is lower in resistance than the high resistance state.

4. The variable resistance nonvolatile memory element writing method according to claim 1,

wherein the first resistance state is a low resistance state, and the second resistance state is a high resistance state that is higher in resistance than the low resistance state.

5. The variable resistance nonvolatile memory element writing method according to claim 1, further comprising

determining whether or not first resistance state writing is completed, the first resistance state writing being writing for changing the variable resistance nonvolatile memory element to the first resistance state by the applying the first voltage pulse set,

wherein the determining is performed after the applying the first voltage pulse set, and

the applying the first voltage pulse set and the determining are repeatedly performed the plurality of times until the variable resistance nonvolatile memory element reaches the first resistance state.

6. The variable resistance nonvolatile memory element writing method according to claim 1, further comprising

applying a second voltage pulse set including a second preliminary voltage pulse and the second voltage pulse to the variable resistance nonvolatile memory element when changing the variable resistance nonvolatile memory element from the first resistance state to the second resistance state, wherein in the second voltage pulse set, the second voltage pulse is applied to the variable resistance nonvolatile memory element subsequent to the second preliminary voltage pulse, the second preliminary voltage pulse being smaller in voltage absolute value than the first threshold voltage and different in polarity from the second voltage pulse.

7. The variable resistance nonvolatile memory element writing method according to claim 6,

wherein the applying the second voltage pulse set is repeatedly performed the plurality of times to change the variable resistance nonvolatile memory element from the first resistance state to the second resistance state.

8. The variable resistance nonvolatile memory element writing method according to claim 6, further comprising:

determining whether or not first resistance state writing is completed, the first resistance state writing being writing for changing the variable resistance nonvolatile memory element to the first resistance state by applying the first voltage pulse in the applying the first voltage pulse set; and

determining whether or not second resistance state writing is completed, the second resistance state writing being writing for changing the variable resistance nonvolatile memory element to the second resistance state by applying the second voltage pulse in the applying the second voltage pulse set,

wherein the determining whether or not the first resistance state writing is completed is performed after the applying the first voltage pulse set,

the determining whether or not the second resistance state writing is completed is performed after the applying the second voltage pulse set,

the applying the first voltage pulse set and the determining whether or not the first resistance state writing is completed are repeatedly performed the plurality of times until the variable resistance nonvolatile memory element reaches the first resistance state, and

the applying the second voltage pulse set and the determining whether or not the second resistance state writing is completed are repeatedly performed the plurality of times until the variable resistance nonvolatile memory element reaches the second resistance state.

9. The variable resistance nonvolatile memory element writing method according to claim 1,

wherein the first transition metal oxide layer and the second transition metal oxide layer comprise a transition metal that is any of tantalum, hafnium, and zirconium.

10. The variable resistance nonvolatile memory element writing method according to claim 1,

wherein the first transition metal oxide layer comprises a first transition metal, and the second transition metal oxide layer comprises a second transition metal different from the first transition metal, and

the second transition metal has a lower standard electrode potential than the first transition metal.

11. The variable resistance nonvolatile memory element writing method according to claim 1,

wherein the first transition metal oxide layer has a composition expressed as TaO_x where 0.8≦

x≦

1.9, and

the second transition metal oxide layer has a composition expressed as TaO_y where x <

y.

12. The variable resistance nonvolatile memory element writing method according to claim 1,

wherein the first preliminary voltage pulse is not zero volts.

13. The variable resistance nonvolatile memory element writing method according to claim 2, further comprising

applying a second voltage pulse set including a second preliminary voltage pulse and the second voltage pulse to the variable resistance nonvolatile memory element when changing the variable resistance nonvolatile memory element from the first resistance state to the second resistance state, wherein in the second voltage pulse set, the second voltage pulse is applied to the variable resistance nonvolatile memory element subsequent to the second preliminary voltage pulse, the second preliminary voltage pulse being smaller in voltage absolute value than the first threshold voltage and different in polarity from the second voltage pulse.

14. The variable resistance nonvolatile memory element writing method according to claim 13,

wherein the applying the second voltage pulse set is repeatedly performed the plurality of times to change the variable resistance nonvolatile memory element from the first resistance state to the second resistance state.

15. The variable resistance nonvolatile memory element writing method according to claim 1, further comprising

repeatedly performing the applying the first voltage pulse set the plurality of times so as to shift current of the memory cell more to a first resistance direction each time first resistance writing is performed, and applying a second voltage pulse set including a second preliminary voltage pulse and the second voltage pulse is equally repeatedly performed the plurality of times so as to shift the current of the memory cell more to a second resistance direction each time second resistance writing is performed, wherein in the second voltage pulse set, the second voltage pulse is applied subsequent to the second preliminary voltage pulse.

16. A variable resistance nonvolatile memory device comprising:

a memory cell including a variable resistance nonvolatile memory element; and

a write control unit configured to, by applying a voltage pulse to the memory cell, perform writing for reversibly changing the variable resistance nonvolatile memory element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse,

wherein the variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer placed between the first electrode and the second electrode,

the variable resistance layer includes an oxygen-deficient first transition metal oxide layer that is in contact with the first electrode, and a second transition metal oxide layer that is in contact with the second electrode and is lower in oxygen deficiency than the first transition metal oxide layer,

the variable resistance nonvolatile memory element has characteristics of changing to the first resistance state when, with respect to one of the first electrode and the second electrode, a first voltage pulse having a positive potential and equal to or more than a first threshold voltage is applied to an other one of the first electrode and the second electrode, and changing to the second resistance state when, with respect to the other one of the first electrode and the second electrode, a second voltage pulse having a positive potential and equal to or more than a second threshold voltage is applied to the one of the first electrode and the second electrode, and

the write control unit is configured to, during a writing operation, successively apply a first voltage pulse set and a memory cell value measurement a plurality of times, the first voltage pulse set including a first preliminary voltage pulse and the first voltage pulse, wherein in the first voltage pulse set, the first voltage pulse is applied to the variable resistance nonvolatile memory element subsequent to the first preliminary voltage pulse when changing the variable resistance nonvolatile memory element from the second resistance state to the first resistance state, such that a value of the memory cell changes in accordance with each successive application of the first voltage pulse set, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.

17. The variable resistance nonvolatile memory device according to claim 16,

wherein the memory cell further includes a switching element that is connected in series with the variable resistance nonvolatile memory element.

18. The variable resistance nonvolatile memory device according to claim 16,

wherein the first preliminary voltage pulse is not zero volts.