Apparatus and methods including source gates

• US 9,378,839 B2
• Filed: 08/04/2014
• Issued: 06/28/2016
• Est. Priority Date: 08/15/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira, Ahmed, Shafqat, Hasnat, Khaled, Parat, Krishna K.
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US14/451,145
• Publication Number:
  US 20140340963A1
• Time in Patent Office: 694 Days
• Field of Search: 365/185.26, 365/185.23, 365/230.06, 365/185.17, 365/185.18
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Claims

1. A method for operation of a memory device, the method comprising:

biasing a common source to 0 volts;

turning on a first source select gate coupled to a selected string of charge storage devices;

turning off a second source select gate coupled to an unselected string of charge storage devices;

turning on a source gate coupled to both the selected and unselected string of charge storage devices;

biasing, with a read voltage, a selected access line coupled to a selected charge storage device in the selected string of charge storage devices;

biasing a plurality of unselected access lines to a voltage greater than the read voltage, the unselected access lines coupled to charge storage devices not being read; and

biasing a slot, coupled to a semiconductor well of the selected and unselected string of charge storage device, with 0 volts.

2. The method of claim 1, wherein turning on the first source select gate comprises turning on the first source select gate that is coupled between the selected string of charge storage devices and the source gate.

3. The method of claim 2, wherein turning off the second source select gate comprises turning off the second source select gate that is coupled between the unselected string of charge storage devices and the source gate.

4. The method of claim 3, wherein turning on the source gate comprises turning on the source gate that is coupled between the first and second source select gates and the common source.

5. The method of claim 3, wherein turning on the first source select gate comprises biasing a control gate of the first source gate with a first voltage that is greater than 0V.

6. The method of claim 3, wherein turning off the second source select gate comprises biasing a control gate of the second source select gate with a second voltage that is less than the first voltage.

7. The method of claim 1, further comprising:

turning on, with a first voltage, a first drain select gate coupled to the selected string of charge storage devices; and

turning off, with a second voltage, a second drain select gate coupled to the unselected string of charge storage devices, wherein the second voltage is less than the first voltage.

8. The method of claim 7, further comprising biasing a data line coupled to the selected and unselected strings of charge storage devices with a voltage greater than 0V.

9. A method for operation of a memory device, the method comprising:

biasing a common source to 0 volts;

biasing a control gate of a first source select gate, coupled to a selected string of charge storage devices, at a voltage;

biasing a control gate of a second source select gate, coupled to an unselected string of charge storage devices, with the voltage;

turning off a source gate coupled to both the selected and unselected string of charge storage devices;

biasing, with a programming voltage, a selected access line coupled to a selected charge storage device in the selected string of charge storage devices; and

biasing a plurality of unselected access lines to a voltage that is less than the programming voltage, the unselected access lines coupled to charge storage devices not being programmed; and

biasing a slot, coupled to a semiconductor well of the selected and unselected string of charge storage devices, with a voltage in a range of 0V to 2V.

10. The method of claim 9, wherein biasing the slot comprises biasing the slot that is coupled to an implant in the semiconductor well.

11. A method for operation of a memory device, the method comprising:

biasing a common source to 0 volts;

biasing a control gate of a first source select gate, coupled to a selected string of charge storage devices, at a voltage;

biasing a control gate of a second source select gate, coupled to an unselected string of charge storage devices, with the voltage;

turning off a source gate coupled to both the selected and unselected string of charge storage devices;

biasing, with a programming voltage, a selected access line coupled to a selected charge storage device in the selected string of charge storage devices; and

biasing a plurality of unselected access lines to a voltage that is less than the programming voltage, the unselected access lines coupled to charge storage devices not being programmed;

wherein turning on the first and second source select gates comprises biasing control gates of the first and second source select gates with a voltage between 0V and 3V.

12. A method for operation of a memory device, the method comprising:

biasing a common source to 0 volts;

biasing a control gate of a first source select gate, coupled to a selected string of charge storage devices, at a voltage;

biasing a control gate of a second source select gate, coupled to an unselected string of charge storage devices, with the voltage;

turning off a source gate coupled to both the selected and unselected string of charge storage devices;

biasing, with a programming voltage, a selected access line coupled to a selected charge storage device in the selected string of charge storage devices;

biasing a plurality of unselected access lines to a voltage that is less than the programming voltage, the unselected access lines coupled to charge storage devices not being programmed; and

biasing a data line coupled to the selected and unselected strings of charge storage devices with a voltage that is less than 1V.

13. A method for operation of a memory device, the method comprising:

biasing a common source to 0 volts;

biasing a control gate of a first source select gate, coupled to a selected string of charge storage devices, at a voltage;

biasing a control gate of a second source select gate, coupled to an unselected string of charge storage devices, with the voltage;

turning off a source gate coupled to both the selected and unselected string of charge storage devices;

biasing, with a programming voltage, a selected access line coupled to a selected charge storage device in the selected string of charge storage devices; and

biasing a plurality of unselected access lines to a voltage that is less than the programming voltage, the unselected access lines coupled to charge storage devices not being programmed;

wherein biasing the plurality of unselected access lines to the voltage that is less than the programming voltage comprises biasing the plurality of unselected access lines with 10V.

14. A method for operation of a memory device, the method comprising:

biasing a semiconductor well to a first voltage substantially equal to 20V;

biasing a first source select gate, coupled to a selected string of charge storage devices that is coupled to the well, at the first voltage;

biasing a second source select gate, coupled to an unselected string of charge storage devices that is coupled to the well, at the first voltage;

biasing a source gate, coupled to both the selected and unselected string of charge storage devices, at the first voltage;

biasing, with an erase voltage, a selected access line coupled to a selected charge storage device in the selected string of charge storage devices; and

biasing a plurality of unselected access lines, coupled to charge storage devices not being erased, with the erase voltage.

15. The method of claim 14, further comprising biasing a data line, coupled to the selected and unselected string of charge storage devices, at the first voltage.

16. The method of claim 14, wherein biasing, with the erase voltage, the selected access line comprises biasing, with 0V, the selected access line.

17. The method of claim 14, wherein biasing the source gate, coupled to both the selected and unselected strings of charge storage devices comprises biasing the source gate to a voltage that reduces leakage of current to a slot coupled to the semiconductor well.

18. The method of claim 14, further comprising floating any strings of charge storage devices not coupled to the source gate.