Systems and methods for sub-zero threshold characterization in a memory cell

• US 9,378,840 B2
• Filed: 11/20/2013
• Issued: 06/28/2016
• Est. Priority Date: 10/28/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Cai, Yu, Wu, Yunxiang, Haratsch, Erich F.
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US14/085,553
• Publication Number:
  US 20150117097A1
• Time in Patent Office: 951 Days
• Field of Search: 365/148, 365/185.02
• US Class Current: 1/1
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

Systems and methods relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. In one embodiment, the systems and methods may include programming a first cell of a solid state memory device to a negative voltage, programming a second cell of the solid state memory device to a positive voltage, wherein the second cell is adjacent to the first cell, calculating a voltage shift on the negative voltage programmed to the first cell, characterizing a shifted voltage level on the first cell as an interim voltage, and subtracting the voltage shift from the interim voltage to yield an actual voltage on the first cell.

Claims

1. A memory system, the system comprising:

a memory cell characterization circuit operable to;

program a first cell of a solid state memory device to a negative voltage;

program a second cell of the solid state memory device to a positive voltage, wherein the second cell is adjacent to the first cell;

calculate a voltage shift on the negative voltage programmed to the first cell, the voltage shift occurring based on inter-cell interference on the programmed first cell when the second cell is being programmed;

characterize a shifted voltage level on the first cell as an interim voltage; and

subtract the voltage shift from the interim voltage to yield an actual voltage on the first cell.

2. The memory system of claim 1, wherein the voltage level on the first cell is a first voltage level, wherein the positive voltage is a first positive voltage, and wherein the memory cell characterization circuit is further operable to:

write the first cell of the solid state memory device to a second positive voltage;

characterize a second voltage level on the first cell;

write the second cell of the solid state memory device to a third positive voltage, wherein the second cell interferes with the first cell such that the voltage on the first cell is the second positive voltage offset by the voltage shift;

characterize a third voltage level on the first cell; and

subtract the second voltage level from the third voltage level to yield the voltage shift.

3. The memory system of claim 2, wherein the voltage shift includes at least a first interference component and a second interference component, wherein the first interference component is due to interference from the second cell on the first cell, wherein the second memory cell is included in a first wordline adjacent to a defined wordline including the first cell, and wherein the memory cell characterization circuit is further operable to:

write a third cell of the solid state memory device to the first positive voltage, wherein the third cell is included in a second wordline adjacent to the defined wordline, and wherein the third cell results in the second interference component interfering with the first cell.

4. The memory system of claim 2, wherein:

characterizing the first voltage on the first cell to yield the interim voltage includes repeatedly reading the first cell using different values for a first threshold voltage distinguishing between a first state and a second state of the first cell to determine when the output of the first cell changes; and

characterizing the third voltage on the first cell includes repeatedly reading the first cell using different values for a second threshold voltage distinguishing between a third state and a fourth state of the first cell to determine when the output of the first cell changes.

5. The memory system of claim 4, wherein all of the different values of the first threshold voltage are greater than or equal to zero, and wherein all of the different values of the second threshold voltage are greater than or equal to zero.

6. The memory system of claim 1, wherein characterizing the voltage on the first cell to yield the interim voltage comprises:

repeatedly reading the first cell using different values for a threshold voltage distinguishing between a first state and a second state of the first cell to determine when the output of the first cell changes.

7. The memory system of claim 6, wherein all of the different values of the threshold voltage are greater than or equal to zero.

8. The memory system of claim 1, wherein the actual voltage is used to set a threshold value for distinguishing between a first state and a second state of the first memory cell.

9. The memory system of claim 1, wherein the voltage shift includes at least a first interference component and a second interference component, wherein the first interference component is due to interference from the second cell on the first cell, wherein the second memory cell is included in a first wordline adjacent to a defined wordline including the first cell, and wherein the memory cell characterization circuit is further operable to:

write a third cell of the solid state memory device to the positive voltage, wherein the third cell is included in a second wordline adjacent to the defined wordline, and wherein the third cell results in the second interference component interfering with the first cell.

10. The memory system of claim 1, wherein the memory system is implemented as part of an integrated circuit.

11. The memory system of claim 1, wherein the system further comprises:

the solid state memory device, and wherein the memory cell characterization circuit and the solid state memory device are implemented on the same integrated circuit.

12. The memory system of claim 1, wherein the solid state memory device includes a number of flash memory cells.

13. The memory system of claim 12, wherein each of the flash memory cells is able to hold a charge distinguishable as two bits of data.

14. A method for characterizing a solid state memory device, the method comprising:

programming a negative voltage to a first cell of a solid state memory device;

programming a positive voltage to a second cell of the solid state memory device, wherein the second cell is adjacent to the first cell;

calculating a voltage shift on the negative voltage programmed to the first cell, the voltage shift occurring based on inter-cell interference on the programmed first cell when the second cell is being programmed;

characterizing a shifted voltage level on the first cell as an interim voltage; and

subtracting the voltage shift from the interim voltage to yield an actual voltage on the first cell.

15. The method of claim 14, the voltage level on the first cell is a first voltage level, wherein the positive voltage is a first positive voltage, and wherein the method further comprises:

writing a second positive voltage to the first cell of the solid state memory device;

characterizing a second voltage level on the first cell;

writing a third positive voltage to the second cell of the solid state memory device, wherein the second cell interferes with the first cell such that the voltage on the first cell is the second positive voltage offset by the voltage shift;

characterizing a third voltage level on the first cell; and

subtracting the second voltage level from the third voltage level to yield the voltage shift.

16. The method of claim 15, wherein the voltage shift includes at least a first interference component and a second interference component, wherein the first interference component is due to interference from the second cell on the first cell, wherein the second memory cell is included in a first wordline adjacent to a defined wordline including the first cell, and wherein the method further comprises:

writing a third cell of the solid state memory device to the first positive voltage, wherein the third cell is included in a second wordline adjacent to the defined wordline, and wherein the third cell results in the second interference component interfering with the first cell.

17. The method of claim 15, wherein:

characterizing the first voltage on the first cell to yield the interim voltage includes repeatedly reading the first cell using different values for a first threshold voltage distinguishing between a first state and a second state of the first cell to determine when the output of the first cell changes; and

characterizing the third voltage on the first cell includes repeatedly reading the first cell using different values for a second threshold voltage distinguishing between a third state and a fourth state of the first cell to determine when the output of the first cell changes.

18. The method of claim 17, wherein all of the different values of the first threshold voltage are greater than or equal to zero, and wherein all of the different values of the second threshold voltage are greater than or equal to zero.

19. An electronic device, the electronic device including:

a solid state memory device; and

a memory cell characterization circuit operable to;

program a first cell of a solid state memory device to a negative voltage;

program a second cell of the solid state memory device to a positive voltage, wherein the second cell is adjacent to the first cell;

calculate a voltage shift on the negative voltage programmed to the first cell, the voltage shift occurring based on inter-cell interference on the programmed first cell when the second cell is being programmed;

characterize a shifted voltage level on the first cell as an interim voltage; and

subtract the voltage shift from the interim voltage to yield an actual voltage on the first cell.

20. The electronic device of claim 19, wherein the voltage level on the first cell is a first voltage level, wherein the positive voltage is a first positive voltage, and wherein the memory cell characterization circuit is further operable to:

write the first cell of the solid state memory device to a second positive voltage;

characterize a second voltage level on the first cell;

write the second cell of the solid state memory device to a third positive voltage, wherein the second cell interferes with the first cell such that the voltage on the first cell is the second positive voltage offset by the voltage shift;

characterize a third voltage level on the first cell; and

subtract the second voltage level from the third voltage level to yield the voltage shift.