Semiconductor device and method for manufacturing the same

• US 9,378,980 B2
• Filed: 12/10/2015
• Issued: 06/28/2016
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koezuka, Junichi
• Primary Examiner(s): Nicely, Joseph C
• Application Number:
  US14/964,898
• Publication Number:
  US 20160093721A1
• Time in Patent Office: 201 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/425 producing ion implantation
• CPC Class Codes: H01L 21/426 using masks
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation. In the transistor including an oxide semiconductor, oxygen-defect-inducing factors are introduced (added) into an oxide semiconductor layer, whereby the resistance of a source and drain regions are selectively reduced. Oxygen-defect-inducing factors are introduced into the oxide semiconductor layer, whereby oxygen defects serving as donors can be effectively formed in the oxide semiconductor layer. The introduced oxygen-defect-inducing factors are one or more selected from titanium, tungsten, and molybdenum, and are introduced by an ion implantation method.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode layer over the gate insulating layer; and

forming a channel formation region, a source region, and a drain region in the oxide semiconductor layer by introducing elements into the oxide semiconductor layer for selectively forming oxygen defects in the source region and the drain region,

wherein a concentration of the elements of the source region or the drain region is higher than that of the channel formation region, and

wherein the elements are one or more selected from the group consisting of titanium, tungsten, and molybdenum.

2. The method for manufacturing a semiconductor device, according to claim 1, further comprising the steps of:

forming an insulating layer over the gate electrode layer; and

forming a source electrode layer and a drain electrode layer over the insulating layer.

3. The method for manufacturing a semiconductor device, according to claim 1, wherein the channel formation region includes the elements in the step of introducing the elements.

4. The method for manufacturing a semiconductor device, according to claim 1, wherein the elements are introduced by an ion implantation method.

5. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode layer over the gate insulating layer;

forming an insulating layer over the gate electrode layer; and

forming a first region functioning as a source and drain regions, a second region having higher resistance than the first region, and a channel formation region by introducing elements into the oxide semiconductor layer for selectively forming oxygen defects in the first region and the second region;

wherein a concentration of the elements of the first region is higher than that of the channel formation region, and

wherein the elements are one or more selected from the group consisting of titanium, tungsten, and molybdenum.

6. The method for manufacturing a semiconductor device, according to claim 5, further comprising the step of:

forming a source electrode layer and a drain electrode layer over the insulating layer.

7. The method for manufacturing a semiconductor device, according to claim 5, wherein the channel formation region includes the elements in the step of introducing the elements.

8. The method for manufacturing a semiconductor device, according to claim 5, wherein the elements are introduced by an ion implantation method.

9. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode layer over the gate insulating layer;

introducing first elements into a first part of the oxide semiconductor layer by using the gate electrode layer as a mask;

forming an insulating layer over the gate electrode layer;

introducing second elements into a second part of the oxide semiconductor layer by using the gate electrode layer and a part of the insulating layer as a mask;

wherein a first region functioning as source and drain regions, a second region having higher resistance than the first region, and a channel formation region are formed by the steps of introducing the first elements and the second elements,

wherein the second region is between the first region and the channel formation region,

wherein a concentration of the sum of the first elements and the second elements of the first region is higher than that of the channel formation region, and

wherein the first elements and the second elements are one or more selected from the group consisting of titanium, tungsten, and molybdenum.

10. The method for manufacturing a semiconductor device, according to claim 9, further comprising the step of:

forming a source electrode layer and a drain electrode layer over the insulating layer.

11. The method for manufacturing a semiconductor device, according to claim 9, wherein the channel formation region includes the first elements in the step of introducing the first elements.

12. The method for manufacturing a semiconductor device, according to claim 9, wherein the first elements and the second elements are introduced by an ion implantation method.